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Rev Log message Author Age Path
122 New simulation template for cache-less system
Meant for debug, simulation only		 ja_rd 4842d 04h /ion/trunk/src/
113 Added clock frequency generic to MPU module template
(the generics are used by UART submodules)		 ja_rd 4852d 03h /ion/trunk/src/
111 Updated 'hello' code sample:
- Longer simulated time for compatibility to new cache		 ja_rd 4852d 03h /ion/trunk/src/
110 Updated 'opcodes' code sample:
- Longer simulated time for compatibility to new cache		 ja_rd 4852d 03h /ion/trunk/src/
109 Updated memtest code sample:
- Initializes I-cache
- Tests execution from FLASH
- Uses small memory model for faster simulation		 ja_rd 4852d 03h /ion/trunk/src/
107 Adventure demo bootstrap code updated:
- typo fixed
- added basic I-cache initialization code		 ja_rd 4856d 02h /ion/trunk/src/
106 SW samples updated:
- Added batch files for running the SW simulation		 ja_rd 4856d 03h /ion/trunk/src/
104 FIXED typo in last commit for simulation template ja_rd 4860d 17h /ion/trunk/src/
102 ADDED cache control bits to CP0 status register
ADDED cache control outputs		 ja_rd 4860d 18h /ion/trunk/src/
100 Obsolete synthesizable template files removed ja_rd 4885d 03h /ion/trunk/src/
99 Obsolete TB template files removed ja_rd 4885d 03h /ion/trunk/src/
97 CPU rd and wr data address buses unified ja_rd 4885d 03h /ion/trunk/src/
92 'hello' demo updated to use new startup files ja_rd 4895d 23h /ion/trunk/src/
91 FIX: startup files can now be used to run from FLASH or BRAM ja_rd 4895d 23h /ion/trunk/src/
90 Added 'Adventure' demo to be run from the DE-1 FLASH ja_rd 4896d 00h /ion/trunk/src/
89 Added startup and utility functions for 'bare metal' applications running from FLASH, plus linker file ja_rd 4896d 00h /ion/trunk/src/
88 Added UART RX interface to MPU template ja_rd 4896d 00h /ion/trunk/src/
87 Added UART RX interface to MPU template ja_rd 4896d 00h /ion/trunk/src/
86 Adapted TB template to use log trigger address ja_rd 4896d 00h /ion/trunk/src/
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script		 ja_rd 4896d 00h /ion/trunk/src/
78 Code sample 'memtest' adapted to test read from flash ja_rd 4905d 21h /ion/trunk/src/
77 Simulation template now supports simulated flash
Synthesis template adapted to latest cache interface
Python script now supports simulated flash		 ja_rd 4905d 21h /ion/trunk/src/
74 Fixed (harmless) error in simulation template 2 ja_rd 4906d 01h /ion/trunk/src/
67 Deprecated files:
Marked three files as unused, to be removed		 ja_rd 4906d 14h /ion/trunk/src/
66 Code samples:
Updated all code samples to use TB2 template and new memory map		 ja_rd 4906d 14h /ion/trunk/src/
65 Fixed io input mux in MPU template 1 ja_rd 4906d 14h /ion/trunk/src/
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file		 ja_rd 4908d 03h /ion/trunk/src/
56 synthesis mpu template updated:
BRAM is now one 32-bit-wide block instead of 4 8-bitters
(it is read only)
python script updated accordingly		 ja_rd 4908d 16h /ion/trunk/src/
55 First version of cache: stub, 1-word cache
(forgot to commit new mpu template file)		 ja_rd 4908d 16h /ion/trunk/src/
51 Adapted simulation and synth templates for cache module ja_rd 4908d 19h /ion/trunk/src/

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