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[/] [ion/] [trunk/] [vhdl/] - Rev 144

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Rev	Log message	Author	Age	Path
141	BUG FIX in cache: cpu stall logic was missing key case 2nd SW in a (cached) row was not being stalled	ja_rd	4793d 04h	/ion/trunk/vhdl/
140	BUG FIX in cpu: MTCx was using Rs as source instead of Rt BUG FIX in cpu: cached sequences of S* were failing, byte_we logic was wrong	ja_rd	4793d 04h	/ion/trunk/vhdl/
139	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4793d 21h	/ion/trunk/vhdl/
138	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4793d 21h	/ion/trunk/vhdl/
136	Added debug output to synthesizable MPU template, and connected debug signals to LEDs	ja_rd	4793d 21h	/ion/trunk/vhdl/
134	Added 'unmapped access' flag to CPU core, meant for debug mostly. Eventually this flag will trigger an interrupt.	ja_rd	4793d 21h	/ion/trunk/vhdl/
133	First draft of the SDRAM controller (Still unused in the code working base)	ja_rd	4796d 19h	/ion/trunk/vhdl/
132	Fixed bug in stall logic (stall for back-to-back SW instructions was wrong)	ja_rd	4796d 19h	/ion/trunk/vhdl/
129	updated pregenerated demo ('hello')	ja_rd	4796d 19h	/ion/trunk/vhdl/
128	updated precompiled simulation testbench	ja_rd	4796d 19h	/ion/trunk/vhdl/
126	added SDRAM verilog simulation model	ja_rd	4796d 19h	/ion/trunk/vhdl/
121	CPU code reorganized a bit No new logic, just a few swapped lines and new comments	ja_rd	4842d 19h	/ion/trunk/vhdl/
120	Updated main package with lots of wait states for all areas	ja_rd	4851d 22h	/ion/trunk/vhdl/
119	Updated pre-generated simulation and synthesis demos	ja_rd	4851d 22h	/ion/trunk/vhdl/
116	Updated demo 'top' file for DE-1 board - Added reset button debouncing - Added template for using different clock input - Uses clock rate generic	ja_rd	4851d 23h	/ion/trunk/vhdl/
115	Updated Altera CSV file (pin location file) for DE-1 board (Added 27MHz clock input)	ja_rd	4852d 01h	/ion/trunk/vhdl/
114	ADDED: 1st version of real cache	ja_rd	4852d 01h	/ion/trunk/vhdl/
112	Updated simulation package for compatibility to new cache	ja_rd	4852d 03h	/ion/trunk/vhdl/
103	ADDED cache control inputs (unused) to dummy cache	ja_rd	4860d 17h	/ion/trunk/vhdl/
101	FIX: code_rd_vma asserted only after reset is done ADDED cache control bits to CP0 status register ADDED cache control outputs	ja_rd	4860d 17h	/ion/trunk/vhdl/
98	CPU rd and wr data address buses unified	ja_rd	4885d 02h	/ion/trunk/vhdl/
96	CPU rd and wr data address buses unified	ja_rd	4885d 02h	/ion/trunk/vhdl/
95	BUG FIX: cache stub properly handles all kind of cycles now	ja_rd	4895d 23h	/ion/trunk/vhdl/
94	Pregenerated demo 'hello' files updated	ja_rd	4895d 23h	/ion/trunk/vhdl/
85	BUG FIX: log2 function was wrong	ja_rd	4895d 23h	/ion/trunk/vhdl/
84	Added 'trigger address' for file logging to both the vhdl TB and the python script	ja_rd	4895d 23h	/ion/trunk/vhdl/
83	BUG FIX: LHU was not doing sign extension properly BUG FIX: SLTIU decoding was wrong	ja_rd	4895d 23h	/ion/trunk/vhdl/
82	bug fix: SLTI wasn't working properly in some cases	ja_rd	4897d 23h	/ion/trunk/vhdl/
81	Added a wait state to the SRAM area for the DE-1 demo code	ja_rd	4904d 18h	/ion/trunk/vhdl/
80	Stub cache fixed Now supports code refills from static 16- and 8- bit memory Plus many mirror corrections	ja_rd	4904d 18h	/ion/trunk/vhdl/

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[/] [ion/] [trunk/] [vhdl/] - Rev 144

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