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[/] [ion/] [trunk/] [vhdl/] - Rev 177

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Rev Log message Author Age Path
171 CPU bug fix: MFC0 instructions aborted by privilege trap should not modify any register ja_rd 4773d 18h /ion/trunk/vhdl/
162 Fixed stupid mistake in headers (date of project) ja_rd 4780d 07h /ion/trunk/vhdl/
161 Added GPL license info to the vhdl headers
This project is becoming respectable :)		 ja_rd 4780d 07h /ion/trunk/vhdl/
159 bug detected but not fixed in cpu
(1st instruction after entering user mode is executed in kernel mode)		 ja_rd 4781d 16h /ion/trunk/vhdl/
158 removed file from TB directory which was committed by mistake ja_rd 4781d 16h /ion/trunk/vhdl/
157 Bug fix in the missing coprocesor exception.
The CPU was triggering a privilege exception for the mtc0 that went into user mode.
Logging HDL updated		 ja_rd 4783d 02h /ion/trunk/vhdl/
153 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.		 ja_rd 4783d 11h /ion/trunk/vhdl/
152 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.		 ja_rd 4783d 11h /ion/trunk/vhdl/
151 BUG FIX: major bugs fixed in cache module
1.- sram address was wrong (leftover from previous version)
2.- writes to unmapped areas were blocking the cache
3.- Sequence SW,LW produced a RAW data hazard in some cases		 ja_rd 4783d 11h /ion/trunk/vhdl/
145 MAJOR UPDATE: first version of D-Cache ja_rd 4786d 01h /ion/trunk/vhdl/
141 BUG FIX in cache: cpu stall logic was missing key case
2nd SW in a (cached) row was not being stalled		 ja_rd 4787d 15h /ion/trunk/vhdl/
140 BUG FIX in cpu: MTCx was using Rs as source instead of Rt
BUG FIX in cpu: cached sequences of S* were failing, byte_we logic was wrong		 ja_rd 4787d 15h /ion/trunk/vhdl/
139 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4788d 09h /ion/trunk/vhdl/
138 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4788d 09h /ion/trunk/vhdl/
136 Added debug output to synthesizable MPU template, and connected debug signals to LEDs ja_rd 4788d 09h /ion/trunk/vhdl/
134 Added 'unmapped access' flag to CPU core, meant for debug mostly.
Eventually this flag will trigger an interrupt.		 ja_rd 4788d 09h /ion/trunk/vhdl/
133 First draft of the SDRAM controller
(Still unused in the code working base)		 ja_rd 4791d 06h /ion/trunk/vhdl/
132 Fixed bug in stall logic
(stall for back-to-back SW instructions was wrong)		 ja_rd 4791d 07h /ion/trunk/vhdl/
129 updated pregenerated demo ('hello') ja_rd 4791d 07h /ion/trunk/vhdl/
128 updated precompiled simulation testbench ja_rd 4791d 07h /ion/trunk/vhdl/
126 added SDRAM verilog simulation model ja_rd 4791d 07h /ion/trunk/vhdl/
121 CPU code reorganized a bit
No new logic, just a few swapped lines and new comments		 ja_rd 4837d 07h /ion/trunk/vhdl/
120 Updated main package with lots of wait states for all areas ja_rd 4846d 09h /ion/trunk/vhdl/
119 Updated pre-generated simulation and synthesis demos ja_rd 4846d 09h /ion/trunk/vhdl/
116 Updated demo 'top' file for DE-1 board
- Added reset button debouncing
- Added template for using different clock input
- Uses clock rate generic		 ja_rd 4846d 10h /ion/trunk/vhdl/
115 Updated Altera CSV file (pin location file) for DE-1 board
(Added 27MHz clock input)		 ja_rd 4846d 12h /ion/trunk/vhdl/
114 ADDED: 1st version of real cache ja_rd 4846d 13h /ion/trunk/vhdl/
112 Updated simulation package for compatibility to new cache ja_rd 4846d 14h /ion/trunk/vhdl/
103 ADDED cache control inputs (unused) to dummy cache ja_rd 4855d 05h /ion/trunk/vhdl/
101 FIX: code_rd_vma asserted only after reset is done
ADDED cache control bits to CP0 status register
ADDED cache control outputs		 ja_rd 4855d 05h /ion/trunk/vhdl/

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