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[/] [ion/] [trunk/] [vhdl/] - Rev 212

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Rev Log message Author Age Path
212 BUG FIX: sequences of back-to-back I/O reads or writes didn't work.
The stall conditions were wrong for those cases.
Minor cleanup of the comments		 ja_rd 4410d 08h /ion/trunk/vhdl/
211 Included a simulated block of I/O regs in the test bench for easing some cache tests. ja_rd 4410d 08h /ion/trunk/vhdl/
207 Simulation memories now modelled with shared variables and not signals.
This improves simulation speed of large programs (e.g. Adventure) by orders of magnitude		 ja_rd 4689d 04h /ion/trunk/vhdl/
206 Fixed SygnalSpy function calls for compatibility with older versions of Modelsim ja_rd 4689d 04h /ion/trunk/vhdl/
205 Fixed bug in test bench interface to CPU ja_rd 4710d 02h /ion/trunk/vhdl/
201 Minor fixes to code comments ja_rd 4724d 02h /ion/trunk/vhdl/
200 CPU interrupt input changed to 8-bit vector
Other modules changed accordingly
Interrupts still missing; this is just preparing the interface		 ja_rd 4724d 02h /ion/trunk/vhdl/
194 Removed deprecated files from old TB version ja_rd 4725d 18h /ion/trunk/vhdl/
193 Major test bench reorganization:
1.- TB now uses same object code as synthesizable demo.
2.- TB now simulates full MPU system.
3.- Console logging moved to TB package.
4.- Code sample makefiles and modelsim script updated accordingly.		 ja_rd 4725d 18h /ion/trunk/vhdl/
191 Separated object code stuff from mcu entity
Object code related stuff now lives in separate file
Makefiles for code samples updated accordingly
Old mcu template deprecated but still in place		 ja_rd 4730d 04h /ion/trunk/vhdl/
188 updated hello demo mpu file ja_rd 4738d 20h /ion/trunk/vhdl/
171 CPU bug fix: MFC0 instructions aborted by privilege trap should not modify any register ja_rd 4769d 12h /ion/trunk/vhdl/
162 Fixed stupid mistake in headers (date of project) ja_rd 4776d 01h /ion/trunk/vhdl/
161 Added GPL license info to the vhdl headers
This project is becoming respectable :)		 ja_rd 4776d 01h /ion/trunk/vhdl/
159 bug detected but not fixed in cpu
(1st instruction after entering user mode is executed in kernel mode)		 ja_rd 4777d 10h /ion/trunk/vhdl/
158 removed file from TB directory which was committed by mistake ja_rd 4777d 10h /ion/trunk/vhdl/
157 Bug fix in the missing coprocesor exception.
The CPU was triggering a privilege exception for the mtc0 that went into user mode.
Logging HDL updated		 ja_rd 4778d 20h /ion/trunk/vhdl/
153 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.		 ja_rd 4779d 05h /ion/trunk/vhdl/
152 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.		 ja_rd 4779d 05h /ion/trunk/vhdl/
151 BUG FIX: major bugs fixed in cache module
1.- sram address was wrong (leftover from previous version)
2.- writes to unmapped areas were blocking the cache
3.- Sequence SW,LW produced a RAW data hazard in some cases		 ja_rd 4779d 05h /ion/trunk/vhdl/
145 MAJOR UPDATE: first version of D-Cache ja_rd 4781d 19h /ion/trunk/vhdl/
141 BUG FIX in cache: cpu stall logic was missing key case
2nd SW in a (cached) row was not being stalled		 ja_rd 4783d 09h /ion/trunk/vhdl/
140 BUG FIX in cpu: MTCx was using Rs as source instead of Rt
BUG FIX in cpu: cached sequences of S* were failing, byte_we logic was wrong		 ja_rd 4783d 09h /ion/trunk/vhdl/
139 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4784d 03h /ion/trunk/vhdl/
138 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4784d 03h /ion/trunk/vhdl/
136 Added debug output to synthesizable MPU template, and connected debug signals to LEDs ja_rd 4784d 03h /ion/trunk/vhdl/
134 Added 'unmapped access' flag to CPU core, meant for debug mostly.
Eventually this flag will trigger an interrupt.		 ja_rd 4784d 03h /ion/trunk/vhdl/
133 First draft of the SDRAM controller
(Still unused in the code working base)		 ja_rd 4787d 00h /ion/trunk/vhdl/
132 Fixed bug in stall logic
(stall for back-to-back SW instructions was wrong)		 ja_rd 4787d 00h /ion/trunk/vhdl/
129 updated pregenerated demo ('hello') ja_rd 4787d 01h /ion/trunk/vhdl/

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