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[/] [ion/] [trunk/] [vhdl/] - Rev 252

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Rev Log message Author Age Path
252 Extracted COP0 logic to separate module within CPU.
No change in functionality.		 ja_rd 3795d 05h /ion/trunk/vhdl/
251 Extracted COP0 logic to separate module within CPU.
Preliminary step for COP0 refactor.
No change in functionality.		 ja_rd 3795d 18h /ion/trunk/vhdl/
250 Precompiled demo object code package is now the bootloader and not the Hello World demo. ja_rd 4220d 22h /ion/trunk/vhdl/
242 BUG FIX:
The CPU was sometimes fetching a spurious opcode in the 1st cycle after a reset.
The cache now has a 'cache_ready' output which the CPU uses to know when NOT to update its IR.		 ja_rd 4221d 00h /ion/trunk/vhdl/
241 Updated simulation and synthesis object code packages with latest build of 'hello' minidemo. ja_rd 4221d 00h /ion/trunk/vhdl/
240 Added a few comments and minor changes to the DE-1 top entity. ja_rd 4221d 00h /ion/trunk/vhdl/
237 Fixed test bench to work with latest modifications of SoC ja_rd 4221d 04h /ion/trunk/vhdl/
235 Fixed comments in cache module ja_rd 4222d 01h /ion/trunk/vhdl/
234 Added a few GPIO registers to the SoC, updated the DE-1 'top' file to drive the SD interface with the GPIO signals. ja_rd 4222d 01h /ion/trunk/vhdl/
233 Fixed top entity for De-1 demos: Bootstrap BRAM size is now taken from a constant in the obj code package. ja_rd 4240d 13h /ion/trunk/vhdl/
227 Removed modules no longer used:
code_rom_pkg replaced by new package in SoC directory.
RS232 sub-modules replaced by new UART		 ja_rd 4369d 06h /ion/trunk/vhdl/
226 Updated demo and test bench to use new SoC entity. ja_rd 4369d 06h /ion/trunk/vhdl/
225 Added utility functions for the initialization of BRAM memories. ja_rd 4369d 06h /ion/trunk/vhdl/
224 MCU entity gutted and transformed into a SoC entity
Different UART, new generics...		 ja_rd 4369d 06h /ion/trunk/vhdl/
223 MCU entity renamed to SoC, moved to separate SoC directory ja_rd 4369d 06h /ion/trunk/vhdl/
218 UART bug fix: rx_rdy flag must be clear only when reading the rx buffer ja_rd 4373d 05h /ion/trunk/vhdl/
217 Removed another SoC file prematurely committed ja_rd 4379d 20h /ion/trunk/vhdl/
216 First draft of SoC removed.
I'll rename it from mips_mcu in order to keep the svn log.		 ja_rd 4379d 20h /ion/trunk/vhdl/
215 First draft of MIPS SoC
Still unused by any of the code samples.
Eventually will replace the mips_mcu entity		 ja_rd 4379d 20h /ion/trunk/vhdl/
214 Updated pre-generated 'Hello' demo, recompiled and retested with the latest changes. ja_rd 4380d 05h /ion/trunk/vhdl/
212 BUG FIX: sequences of back-to-back I/O reads or writes didn't work.
The stall conditions were wrong for those cases.
Minor cleanup of the comments		 ja_rd 4380d 05h /ion/trunk/vhdl/
211 Included a simulated block of I/O regs in the test bench for easing some cache tests. ja_rd 4380d 05h /ion/trunk/vhdl/
207 Simulation memories now modelled with shared variables and not signals.
This improves simulation speed of large programs (e.g. Adventure) by orders of magnitude		 ja_rd 4659d 01h /ion/trunk/vhdl/
206 Fixed SygnalSpy function calls for compatibility with older versions of Modelsim ja_rd 4659d 01h /ion/trunk/vhdl/
205 Fixed bug in test bench interface to CPU ja_rd 4679d 23h /ion/trunk/vhdl/
201 Minor fixes to code comments ja_rd 4693d 23h /ion/trunk/vhdl/
200 CPU interrupt input changed to 8-bit vector
Other modules changed accordingly
Interrupts still missing; this is just preparing the interface		 ja_rd 4693d 23h /ion/trunk/vhdl/
194 Removed deprecated files from old TB version ja_rd 4695d 15h /ion/trunk/vhdl/
193 Major test bench reorganization:
1.- TB now uses same object code as synthesizable demo.
2.- TB now simulates full MPU system.
3.- Console logging moved to TB package.
4.- Code sample makefiles and modelsim script updated accordingly.		 ja_rd 4695d 15h /ion/trunk/vhdl/
191 Separated object code stuff from mcu entity
Object code related stuff now lives in separate file
Makefiles for code samples updated accordingly
Old mcu template deprecated but still in place		 ja_rd 4700d 00h /ion/trunk/vhdl/

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