URL https://opencores.org/ocsvn/ion/ion/trunk

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[/] [ion/] [trunk/] [vhdl/] - Rev 65

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Rev	Log message	Author	Age	Path
64	Refactored memory decoding logic (wait states and read-only attributes unimplemented yet)	ja_rd	4891d 18h	/ion/trunk/vhdl/
63	DE-1 demo top module: added registers for SD interface, switches and 7-seg display	ja_rd	4891d 18h	/ion/trunk/vhdl/
62	CPU fixed: fixed bug in EPC load logic relative to mem_wait stalls parametrized reset and trap vector addresses	ja_rd	4891d 18h	/ion/trunk/vhdl/
60	Forgot to upload new TB package!! Without this, simulations don't work...	ja_rd	4891d 18h	/ion/trunk/vhdl/
59	cleaned up top vhdl module of demo moved reset sync ff chain to top module updated pre-generated demo file	ja_rd	4893d 07h	/ion/trunk/vhdl/
58	Cleaned up cache stub code	ja_rd	4893d 18h	/ion/trunk/vhdl/
57	updated precompiled demo: single 32-bit BROM instead of 4x8-bit	ja_rd	4893d 20h	/ion/trunk/vhdl/
48	Temporary fix to memory decoding constants	ja_rd	4893d 23h	/ion/trunk/vhdl/
47	Pre-generated simulation test benches updated	ja_rd	4893d 23h	/ion/trunk/vhdl/
46	First version of cache: stub, 1-word cache Stub cache tested on simulation and HW, just a stub Adapted CPU stall logic to 1st version of cache Adapted all other modules for compatibility with cache	ja_rd	4893d 23h	/ion/trunk/vhdl/
43	added comments to dummy 'cache' stub	ja_rd	4896d 07h	/ion/trunk/vhdl/
42	Added cache stub module, plus related test bench	ja_rd	4898d 02h	/ion/trunk/vhdl/
40	pre-generated 'hello' demo updated	ja_rd	4898d 02h	/ion/trunk/vhdl/
37	functions added to package for standard address decoding	ja_rd	4898d 03h	/ion/trunk/vhdl/
36	pre-generated simulation test bench TB1 updated for compatibility to other changes	ja_rd	4898d 03h	/ion/trunk/vhdl/
35	CPU mem_wait logic updated to work with cache	ja_rd	4898d 03h	/ion/trunk/vhdl/
30	Completed decoding of instructions (to prevent side effects of invalid opcodes)	ja_rd	4900d 00h	/ion/trunk/vhdl/
28	Core updated: supports CP0 cause register and traps in delay slots traps abort next instruction in all cases (incl. jumps/L/S)	ja_rd	4900d 01h	/ion/trunk/vhdl/
23	Unimplemented instruction are now trapped (barely tested)	ja_rd	4900d 06h	/ion/trunk/vhdl/
22	FIXED killer bug in instruction decoder for beq & mfc0 Decoding was incomplete and beq was using wrong ALU input	ja_rd	4901d 03h	/ion/trunk/vhdl/
21	Converted multiplier module reset to synchronous	ja_rd	4901d 14h	/ion/trunk/vhdl/
18	pre-generated simulation test bench 'hello world' adapted to new mult module	ja_rd	4901d 16h	/ion/trunk/vhdl/
12	Adapted multiplier unit from Plasma	ja_rd	4901d 16h	/ion/trunk/vhdl/
8	Trap handling now works as in the MIPS specs: EPC points to victim instruction (break/syscall)	ja_rd	4902d 18h	/ion/trunk/vhdl/
6	Fix: BREAK now aborts load and jump instructions properly	ja_rd	4902d 20h	/ion/trunk/vhdl/
2	First commit (includes 'hello' demo)	ja_rd	4903d 06h	/ion/trunk/vhdl/

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[/] [ion/] [trunk/] [vhdl/] - Rev 65

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