OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] - Rev 86

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
85 BUG FIX: log2 function was wrong ja_rd 4880d 23h /ion/trunk/vhdl/
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script		 ja_rd 4880d 23h /ion/trunk/vhdl/
83 BUG FIX: LHU was not doing sign extension properly
BUG FIX: SLTIU decoding was wrong		 ja_rd 4880d 23h /ion/trunk/vhdl/
82 bug fix: SLTI wasn't working properly in some cases ja_rd 4883d 00h /ion/trunk/vhdl/
81 Added a wait state to the SRAM area for the DE-1 demo code ja_rd 4889d 18h /ion/trunk/vhdl/
80 Stub cache fixed
Now supports code refills from static 16- and 8- bit memory
Plus many mirror corrections		 ja_rd 4889d 18h /ion/trunk/vhdl/
76 Adapted pregenerated vhdl files to latest changes ja_rd 4890d 21h /ion/trunk/vhdl/
75 Added support for 8-bit-wide static memory (e.g. Flash)
Updated demo 'top' file to use the DE-1 onboard flash		 ja_rd 4890d 21h /ion/trunk/vhdl/
74 Fixed (harmless) error in simulation template 2 ja_rd 4891d 01h /ion/trunk/vhdl/
73 Fixed comment about write cycles in cache module ja_rd 4891d 01h /ion/trunk/vhdl/
72 Fixed stupid bug in SRAM write cycles (setup time violated)
Wait states implemented for SRAM wait and read cycles		 ja_rd 4891d 01h /ion/trunk/vhdl/
68 Updated pre-generated vhdl files ja_rd 4891d 13h /ion/trunk/vhdl/
64 Refactored memory decoding logic
(wait states and read-only attributes unimplemented yet)		 ja_rd 4891d 13h /ion/trunk/vhdl/
63 DE-1 demo top module:
added registers for SD interface, switches and 7-seg display		 ja_rd 4891d 13h /ion/trunk/vhdl/
62 CPU fixed:
fixed bug in EPC load logic relative to mem_wait stalls
parametrized reset and trap vector addresses		 ja_rd 4891d 13h /ion/trunk/vhdl/
60 Forgot to upload new TB package!!
Without this, simulations don't work...		 ja_rd 4891d 14h /ion/trunk/vhdl/
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file		 ja_rd 4893d 03h /ion/trunk/vhdl/
58 Cleaned up cache stub code ja_rd 4893d 14h /ion/trunk/vhdl/
57 updated precompiled demo:
single 32-bit BROM instead of 4x8-bit		 ja_rd 4893d 15h /ion/trunk/vhdl/
48 Temporary fix to memory decoding constants ja_rd 4893d 19h /ion/trunk/vhdl/
47 Pre-generated simulation test benches updated ja_rd 4893d 19h /ion/trunk/vhdl/
46 First version of cache: stub, 1-word cache
Stub cache tested on simulation and HW, just a stub
Adapted CPU stall logic to 1st version of cache
Adapted all other modules for compatibility with cache		 ja_rd 4893d 19h /ion/trunk/vhdl/
43 added comments to dummy 'cache' stub ja_rd 4896d 03h /ion/trunk/vhdl/
42 Added cache stub module, plus related test bench ja_rd 4897d 22h /ion/trunk/vhdl/
40 pre-generated 'hello' demo updated ja_rd 4897d 22h /ion/trunk/vhdl/
37 functions added to package for standard address decoding ja_rd 4897d 23h /ion/trunk/vhdl/
36 pre-generated simulation test bench TB1 updated
for compatibility to other changes		 ja_rd 4897d 23h /ion/trunk/vhdl/
35 CPU mem_wait logic updated to work with cache ja_rd 4897d 23h /ion/trunk/vhdl/
30 Completed decoding of instructions
(to prevent side effects of invalid opcodes)		 ja_rd 4899d 20h /ion/trunk/vhdl/
28 Core updated:
supports CP0 cause register and traps in delay slots
traps abort next instruction in all cases (incl. jumps/L*/S*)		 ja_rd 4899d 21h /ion/trunk/vhdl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.