URL https://opencores.org/ocsvn/ion/ion/trunk

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[/] [ion/] [trunk/] [vhdl/] [demo/] - Rev 191

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Rev	Log message	Author	Age	Path
191	Separated object code stuff from mcu entity Object code related stuff now lives in separate file Makefiles for code samples updated accordingly Old mcu template deprecated but still in place	ja_rd	4752d 18h	/ion/trunk/vhdl/demo/
188	updated hello demo mpu file	ja_rd	4761d 11h	/ion/trunk/vhdl/demo/
162	Fixed stupid mistake in headers (date of project)	ja_rd	4798d 15h	/ion/trunk/vhdl/demo/
161	Added GPL license info to the vhdl headers This project is becoming respectable :)	ja_rd	4798d 15h	/ion/trunk/vhdl/demo/
138	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4806d 17h	/ion/trunk/vhdl/demo/
136	Added debug output to synthesizable MPU template, and connected debug signals to LEDs	ja_rd	4806d 17h	/ion/trunk/vhdl/demo/
129	updated pregenerated demo ('hello')	ja_rd	4809d 15h	/ion/trunk/vhdl/demo/
119	Updated pre-generated simulation and synthesis demos	ja_rd	4864d 18h	/ion/trunk/vhdl/demo/
116	Updated demo 'top' file for DE-1 board - Added reset button debouncing - Added template for using different clock input - Uses clock rate generic	ja_rd	4864d 19h	/ion/trunk/vhdl/demo/
115	Updated Altera CSV file (pin location file) for DE-1 board (Added 27MHz clock input)	ja_rd	4864d 21h	/ion/trunk/vhdl/demo/
98	CPU rd and wr data address buses unified	ja_rd	4897d 22h	/ion/trunk/vhdl/demo/
94	Pregenerated demo 'hello' files updated	ja_rd	4908d 19h	/ion/trunk/vhdl/demo/
76	Adapted pregenerated vhdl files to latest changes	ja_rd	4918d 16h	/ion/trunk/vhdl/demo/
75	Added support for 8-bit-wide static memory (e.g. Flash) Updated demo 'top' file to use the DE-1 onboard flash	ja_rd	4918d 16h	/ion/trunk/vhdl/demo/
68	Updated pre-generated vhdl files	ja_rd	4919d 09h	/ion/trunk/vhdl/demo/
63	DE-1 demo top module: added registers for SD interface, switches and 7-seg display	ja_rd	4919d 09h	/ion/trunk/vhdl/demo/
59	cleaned up top vhdl module of demo moved reset sync ff chain to top module updated pre-generated demo file	ja_rd	4920d 23h	/ion/trunk/vhdl/demo/
57	updated precompiled demo: single 32-bit BROM instead of 4x8-bit	ja_rd	4921d 11h	/ion/trunk/vhdl/demo/
46	First version of cache: stub, 1-word cache Stub cache tested on simulation and HW, just a stub Adapted CPU stall logic to 1st version of cache Adapted all other modules for compatibility with cache	ja_rd	4921d 15h	/ion/trunk/vhdl/demo/
40	pre-generated 'hello' demo updated	ja_rd	4925d 18h	/ion/trunk/vhdl/demo/
2	First commit (includes 'hello' demo)	ja_rd	4930d 22h	/ion/trunk/vhdl/demo/

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[/] [ion/] [trunk/] [vhdl/] [demo/] - Rev 191

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