| Rev |
Log message |
Author |
Age |
Path |
| 102 |
GNU GDB FTP has renamed gdb-6.8 package to gdb-6.8a package. Uncompressed it remains gdb-6.8, so no other changes to script are necessary. |
rfajardo |
4621d 12h |
/minsoc/branches/verilator/ |
| 101 |
Documentation, wiki's address updated. |
rfajardo |
4647d 00h |
/minsoc/branches/verilator/ |
| 100 |
syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. |
rfajardo |
4655d 22h |
/minsoc/branches/verilator/ |
| 99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
4655d 22h |
/minsoc/branches/verilator/ |
| 98 |
Removing deprecated minsoc_top.qsf file. |
rfajardo |
4655d 23h |
/minsoc/branches/verilator/ |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4655d 23h |
/minsoc/branches/verilator/ |
| 96 |
Some files needed for Altera synthesis |
javieralso |
4656d 09h |
/minsoc/branches/verilator/ |
| 95 |
Makefile for Altera FPGAs fixed |
javieralso |
4657d 13h |
/minsoc/branches/verilator/ |
| 94 |
Fix bug in minsoc_top.prj for Altera synthesis |
javieralso |
4659d 21h |
/minsoc/branches/verilator/ |
| 93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
4660d 00h |
/minsoc/branches/verilator/ |
| 92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
4660d 22h |
/minsoc/branches/verilator/ |
| 91 |
prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. |
rfajardo |
4660d 23h |
/minsoc/branches/verilator/ |
| 90 |
After minsoc_top.prj update, make regenerated src and xst files. |
rfajardo |
4661d 14h |
/minsoc/branches/verilator/ |
| 89 |
minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. |
rfajardo |
4661d 14h |
/minsoc/branches/verilator/ |
| 88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
4661d 15h |
/minsoc/branches/verilator/ |
| 87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
4661d 16h |
/minsoc/branches/verilator/ |
| 86 |
Updating configure script messages. |
rfajardo |
4661d 16h |
/minsoc/branches/verilator/ |
| 85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
4661d 16h |
/minsoc/branches/verilator/ |
| 84 |
syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v |
rfajardo |
4662d 17h |
/minsoc/branches/verilator/ |
| 83 |
minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. |
rfajardo |
4673d 22h |
/minsoc/branches/verilator/ |
| 82 |
minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. |
rfajardo |
4676d 21h |
/minsoc/branches/verilator/ |
| 81 |
Installation script complete, nice text feedback, output logs and better execution order. |
rfajardo |
4677d 08h |
/minsoc/branches/verilator/ |
| 80 |
Establishing a better Makefile system for firmwares. |
rfajardo |
4679d 21h |
/minsoc/branches/verilator/ |
| 79 |
minsoc-install.sh: rpath corrected.
required-cygwin-tools: updated |
rfajardo |
4680d 13h |
/minsoc/branches/verilator/ |
| 78 |
minsoc-install.sh: Advanced JTAG bridge compilation needs to know where the dynamic libraries are on runtime. Patching (sed) the Makefile to compile it with the rpath to the libraries (libusb/libftdi). |
rfajardo |
4680d 14h |
/minsoc/branches/verilator/ |
| 77 |
New tool requirements for installing Icarus Verilog. |
rfajardo |
4680d 14h |
/minsoc/branches/verilator/ |
| 76 |
Including a script allowing the installation of MinSoC and all its required tools.
It should be working for all Linuxes and Cygwin. |
rfajardo |
4680d 14h |
/minsoc/branches/verilator/ |
| 75 |
Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules and define file of ethmac ip core. |
rfajardo |
4687d 14h |
/minsoc/branches/verilator/ |
| 74 |
or1200.h includes a CLABLE macro which uses __USER_LABEL_PREFIX__(from compiler defined macro) to find out if we need the underscore as prefix to reference C functions (its assembly labels) or not.
except.S and reset.S use CLABLE to call externally defined C functions.
This should avoid problems compiling firmware with old or new toolchain.
support/common.mk updated, reset-nocache.o and reset-icdc.o are dependent on or1200.h |
rfajardo |
4780d 13h |
/minsoc/branches/verilator/ |
| 73 |
Makefile does not automatic clean anymore. In Windows rm -f leads to errors and abort synthesis.
minsoc/syn/setup.bat added. Asks for Xilinx settings32|64.bat script and completely implements MinSoC. On completion or error, it holds window open until user input ENTER.
minsoc/sim/modelsim/: *.bat holds window open until user input ENTER.
run_sim.bat asks for target firmware, check if it exists before running simulator. Holds window open and output error message if not found. Does not hold for simulator. |
rfajardo |
4780d 18h |
/minsoc/branches/verilator/ |
