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URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

[/] [mkjpeg/] [trunk/] [design/] - Rev 71

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Rev Log message Author Age Path
71 write memory selection pipeline delay correction mikel262 4260d 08h /mkjpeg/trunk/design/
67 mikel262 4669d 09h /mkjpeg/trunk/design/
66 memory initialization updated mikel262 4805d 10h /mkjpeg/trunk/design/
65 Added VHDL equivalent for Verilog's HeaderRAM.v mikel262 4947d 19h /mkjpeg/trunk/design/
63 Added YUV input support. mikel262 5257d 05h /mkjpeg/trunk/design/
61 Design now uses 4:2:2 chroma subsampling mikel262 5298d 19h /mkjpeg/trunk/design/
58 fix for C_EXTRA_LINES=0 mikel262 5301d 09h /mkjpeg/trunk/design/
57 default max performance mikel262 5301d 20h /mkjpeg/trunk/design/
56 BUF_FIFO redesign, for memory/performance tradeoff mikel262 5301d 20h /mkjpeg/trunk/design/
52 Redesigned BUF_FIFO.vhd to significantly reduce area utilization.
Only memory optimized version now possible.		 mikel262 5312d 21h /mkjpeg/trunk/design/
51 fix in buf fifo (synthesis problem) mikel262 5316d 20h /mkjpeg/trunk/design/
50 mikel262 5317d 05h /mkjpeg/trunk/design/
49 Added 16 bit RGB 565 input format. mikel262 5317d 05h /mkjpeg/trunk/design/
46 x1 mikel262 5326d 08h /mkjpeg/trunk/design/
44 stall re-added mikel262 5326d 08h /mkjpeg/trunk/design/
43 stall readded mikel262 5326d 08h /mkjpeg/trunk/design/
42 Added backpressure/stallability of output interface. mikel262 5329d 19h /mkjpeg/trunk/design/
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5467d 07h /mkjpeg/trunk/design/
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5509d 22h /mkjpeg/trunk/design/
39 bug fix. mikel262 5512d 20h /mkjpeg/trunk/design/
38 Reduced processing latency of Huffman encoding mikel262 5537d 20h /mkjpeg/trunk/design/
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5542d 00h /mkjpeg/trunk/design/
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5543d 20h /mkjpeg/trunk/design/
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5544d 17h /mkjpeg/trunk/design/
32 mikel262 5545d 21h /mkjpeg/trunk/design/
31 Specification update, minor area improvements in BUF_FIFO. mikel262 5548d 22h /mkjpeg/trunk/design/
30 mikel262 5549d 10h /mkjpeg/trunk/design/
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5549d 18h /mkjpeg/trunk/design/
25 moved from branch to trunk mikel262 5552d 07h /mkjpeg/trunk/design/

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