OpenCores
URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] - Rev 122

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
122 Added comment to explain why c_bus isn't delayed but reg_dest is delayed. rhoads 7474d 07h /mlite/trunk/vhdl/
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7485d 19h /mlite/trunk/vhdl/
120 Make generics "GENERIC" rhoads 7485d 19h /mlite/trunk/vhdl/
119 Opcodes from count.c rhoads 7524d 06h /mlite/trunk/vhdl/
118 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7524d 06h /mlite/trunk/vhdl/
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7524d 06h /mlite/trunk/vhdl/
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7524d 06h /mlite/trunk/vhdl/
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7524d 06h /mlite/trunk/vhdl/
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7524d 06h /mlite/trunk/vhdl/
113 Matthias Grunewald's bug fixes:
Branch and compare instructions didn't interpret immediate as signed.		 rhoads 7524d 07h /mlite/trunk/vhdl/
112 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7524d 07h /mlite/trunk/vhdl/
108 changed interrupt vector from 0x30 to 0x3c rhoads 7798d 03h /mlite/trunk/vhdl/
107 merged rising_edge(clk) statements rhoads 7798d 03h /mlite/trunk/vhdl/
106 better test mem_pause rhoads 7801d 05h /mlite/trunk/vhdl/
105 better test mem_pause rhoads 7801d 05h /mlite/trunk/vhdl/
103 shorten similation times rhoads 7802d 04h /mlite/trunk/vhdl/
102 permit testing mem_pause rhoads 7802d 04h /mlite/trunk/vhdl/
101 Correctly freeze the pipeline when mem_pause = '1' rhoads 7802d 05h /mlite/trunk/vhdl/
99 correct upper 32-bits for mult(-1,-1) rhoads 7944d 04h /mlite/trunk/vhdl/
98 Fix size of GENERIC ram. rhoads 7949d 03h /mlite/trunk/vhdl/
97 added documentation rhoads 8013d 08h /mlite/trunk/vhdl/
96 Simplify take_branch rhoads 8047d 10h /mlite/trunk/vhdl/
95 register mem_write and mem_byte_sel for speed calculations rhoads 8047d 10h /mlite/trunk/vhdl/
93 make run now runs for 500 us rhoads 8049d 04h /mlite/trunk/vhdl/
92 Updated rhoads 8049d 04h /mlite/trunk/vhdl/
91 Removed unused alu_function_type entries rhoads 8049d 04h /mlite/trunk/vhdl/
90 Now multiplies two bits at a time rhoads 8049d 04h /mlite/trunk/vhdl/
89 Use address_reg instead of address_data to break timing slow down rhoads 8049d 04h /mlite/trunk/vhdl/
88 Cleanup spaces rhoads 8049d 04h /mlite/trunk/vhdl/
87 Seperated left and right shift variables rhoads 8049d 04h /mlite/trunk/vhdl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.