OpenCores
URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] - Rev 129

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
129 Added reset_in to sensitivity list rhoads 7198d 12h /mlite/trunk/vhdl/
128 Reset all registers, constants now upper case. rhoads 7316d 23h /mlite/trunk/vhdl/
125 Fixed pc_source_type comment. rhoads 7335d 12h /mlite/trunk/vhdl/
124 Holger Lohn's fix for interrupts when 3-state pipeline enabled. rhoads 7335d 12h /mlite/trunk/vhdl/
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7402d 13h /mlite/trunk/vhdl/
122 Added comment to explain why c_bus isn't delayed but reg_dest is delayed. rhoads 7466d 13h /mlite/trunk/vhdl/
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7478d 02h /mlite/trunk/vhdl/
120 Make generics "GENERIC" rhoads 7478d 02h /mlite/trunk/vhdl/
119 Opcodes from count.c rhoads 7516d 13h /mlite/trunk/vhdl/
118 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7516d 13h /mlite/trunk/vhdl/
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7516d 13h /mlite/trunk/vhdl/
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7516d 13h /mlite/trunk/vhdl/
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7516d 13h /mlite/trunk/vhdl/
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7516d 13h /mlite/trunk/vhdl/
113 Matthias Grunewald's bug fixes:
Branch and compare instructions didn't interpret immediate as signed.		 rhoads 7516d 13h /mlite/trunk/vhdl/
112 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7516d 13h /mlite/trunk/vhdl/
108 changed interrupt vector from 0x30 to 0x3c rhoads 7790d 09h /mlite/trunk/vhdl/
107 merged rising_edge(clk) statements rhoads 7790d 09h /mlite/trunk/vhdl/
106 better test mem_pause rhoads 7793d 12h /mlite/trunk/vhdl/
105 better test mem_pause rhoads 7793d 12h /mlite/trunk/vhdl/
103 shorten similation times rhoads 7794d 11h /mlite/trunk/vhdl/
102 permit testing mem_pause rhoads 7794d 11h /mlite/trunk/vhdl/
101 Correctly freeze the pipeline when mem_pause = '1' rhoads 7794d 11h /mlite/trunk/vhdl/
99 correct upper 32-bits for mult(-1,-1) rhoads 7936d 10h /mlite/trunk/vhdl/
98 Fix size of GENERIC ram. rhoads 7941d 09h /mlite/trunk/vhdl/
97 added documentation rhoads 8005d 14h /mlite/trunk/vhdl/
96 Simplify take_branch rhoads 8039d 16h /mlite/trunk/vhdl/
95 register mem_write and mem_byte_sel for speed calculations rhoads 8039d 16h /mlite/trunk/vhdl/
93 make run now runs for 500 us rhoads 8041d 10h /mlite/trunk/vhdl/
92 Updated rhoads 8041d 10h /mlite/trunk/vhdl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.