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[/] [mlite/] [trunk/] [vhdl/] - Rev 196

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Rev Log message Author Age Path
196 Explained how to remove mult.vhd and use SW multiplication and division. rhoads 6374d 03h /mlite/trunk/vhdl/
194 Implemented BREAK and SYSCALL opcodes rhoads 6391d 06h /mlite/trunk/vhdl/
186 Change memory_type to "XILINX_16X" rhoads 6408d 00h /mlite/trunk/vhdl/
185 Latest opcodes from count.c rhoads 6423d 02h /mlite/trunk/vhdl/
184 Fix comment rhoads 6423d 02h /mlite/trunk/vhdl/
181 Fix typo in comment rhoads 6423d 03h /mlite/trunk/vhdl/
180 Easily permit full UART simulation rhoads 6423d 04h /mlite/trunk/vhdl/
139 Major changes -- updated to Plasma Version 3 rhoads 6736d 23h /mlite/trunk/vhdl/
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7216d 22h /mlite/trunk/vhdl/
131 Changed "GENERIC" to "DEFAULT" to be Xilinx friendly. rhoads 7216d 22h /mlite/trunk/vhdl/
129 Added reset_in to sensitivity list rhoads 7235d 22h /mlite/trunk/vhdl/
128 Reset all registers, constants now upper case. rhoads 7354d 09h /mlite/trunk/vhdl/
125 Fixed pc_source_type comment. rhoads 7372d 23h /mlite/trunk/vhdl/
124 Holger Lohn's fix for interrupts when 3-state pipeline enabled. rhoads 7372d 23h /mlite/trunk/vhdl/
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7439d 23h /mlite/trunk/vhdl/
122 Added comment to explain why c_bus isn't delayed but reg_dest is delayed. rhoads 7504d 00h /mlite/trunk/vhdl/
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7515d 12h /mlite/trunk/vhdl/
120 Make generics "GENERIC" rhoads 7515d 12h /mlite/trunk/vhdl/
119 Opcodes from count.c rhoads 7553d 23h /mlite/trunk/vhdl/
118 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7553d 23h /mlite/trunk/vhdl/
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7553d 23h /mlite/trunk/vhdl/
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7553d 23h /mlite/trunk/vhdl/
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7553d 23h /mlite/trunk/vhdl/
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7553d 23h /mlite/trunk/vhdl/
113 Matthias Grunewald's bug fixes:
Branch and compare instructions didn't interpret immediate as signed.		 rhoads 7553d 23h /mlite/trunk/vhdl/
112 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7553d 23h /mlite/trunk/vhdl/
108 changed interrupt vector from 0x30 to 0x3c rhoads 7827d 20h /mlite/trunk/vhdl/
107 merged rising_edge(clk) statements rhoads 7827d 20h /mlite/trunk/vhdl/
106 better test mem_pause rhoads 7830d 22h /mlite/trunk/vhdl/
105 better test mem_pause rhoads 7830d 22h /mlite/trunk/vhdl/

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