Rev |
Log message |
Author |
Age |
Path |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4342d 05h |
/mod_sim_exp/ |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4342d 06h |
/mod_sim_exp/ |
29 |
added software for generation of test input for the tesbenches |
JonasDC |
4342d 19h |
/mod_sim_exp/ |
28 |
updated makefile for new pipeline sources |
JonasDC |
4342d 19h |
/mod_sim_exp/ |
27 |
test input values for multiplier_tb |
JonasDC |
4342d 19h |
/mod_sim_exp/ |
26 |
testbench for only the montgommery multiplier |
JonasDC |
4342d 19h |
/mod_sim_exp/ |
25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4342d 19h |
/mod_sim_exp/ |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4346d 04h |
/mod_sim_exp/ |
23 |
added descriptive comments |
JonasDC |
4346d 06h |
/mod_sim_exp/ |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4348d 23h |
/mod_sim_exp/ |
21 |
changed x_i signal to xi |
JonasDC |
4350d 07h |
/mod_sim_exp/ |
20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4350d 07h |
/mod_sim_exp/ |
19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4355d 02h |
/mod_sim_exp/ |
18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4356d 02h |
/mod_sim_exp/ |
17 |
updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules |
JonasDC |
4356d 07h |
/mod_sim_exp/ |
16 |
package with modified generic parameter for register_n |
JonasDC |
4356d 20h |
/mod_sim_exp/ |
15 |
changed generic for register width from n to width for consistency |
JonasDC |
4356d 20h |
/mod_sim_exp/ |
14 |
changed comments, file is now according to OC design rules |
JonasDC |
4356d 20h |
/mod_sim_exp/ |
13 |
added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules |
JonasDC |
4356d 20h |
/mod_sim_exp/ |
12 |
updated comments, file is now completely according to design rules |
JonasDC |
4356d 21h |
/mod_sim_exp/ |
11 |
simulation output folder |
JonasDC |
4356d 23h |
/mod_sim_exp/ |
10 |
changed signal input port names to correct name |
JonasDC |
4357d 01h |
/mod_sim_exp/ |
9 |
added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names |
JonasDC |
4357d 01h |
/mod_sim_exp/ |
8 |
added descriptive comments |
JonasDC |
4357d 04h |
/mod_sim_exp/ |
7 |
Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments |
JonasDC |
4357d 04h |
/mod_sim_exp/ |
6 |
Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments |
JonasDC |
4357d 04h |
/mod_sim_exp/ |
5 |
not needed on svn, is generated by testbench |
JonasDC |
4357d 04h |
/mod_sim_exp/ |
4 |
Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments |
JonasDC |
4357d 06h |
/mod_sim_exp/ |
3 |
updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation |
JonasDC |
4357d 20h |
/mod_sim_exp/ |
2 |
First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. |
JonasDC |
4362d 02h |
/mod_sim_exp/ |