URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.0/] [rtl/] - Rev 104

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
100	added version 1.0 tag for completeness. This version is the first version that is adapted to the opencores design rules. Also the code is cleaned up. previous tag was incorrect, now updated	JonasDC	3964d 19h	/mod_sim_exp/tags/Release_1.0/rtl/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4237d 15h	/mod_sim_exp/trunk/rtl/
23	added descriptive comments	JonasDC	4237d 16h	/mod_sim_exp/trunk/rtl/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4240d 10h	/mod_sim_exp/trunk/rtl/
21	changed x_i signal to xi	JonasDC	4241d 18h	/mod_sim_exp/trunk/rtl/
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4241d 18h	/mod_sim_exp/trunk/rtl/
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4246d 13h	/mod_sim_exp/trunk/rtl/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4247d 13h	/mod_sim_exp/trunk/rtl/
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4247d 18h	/mod_sim_exp/trunk/rtl/
16	package with modified generic parameter for register_n	JonasDC	4248d 07h	/mod_sim_exp/trunk/rtl/
15	changed generic for register width from n to width for consistency	JonasDC	4248d 07h	/mod_sim_exp/trunk/rtl/
14	changed comments, file is now according to OC design rules	JonasDC	4248d 07h	/mod_sim_exp/trunk/rtl/
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4248d 07h	/mod_sim_exp/trunk/rtl/
12	updated comments, file is now completely according to design rules	JonasDC	4248d 07h	/mod_sim_exp/trunk/rtl/
10	changed signal input port names to correct name	JonasDC	4248d 12h	/mod_sim_exp/trunk/rtl/
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4248d 12h	/mod_sim_exp/trunk/rtl/
8	added descriptive comments	JonasDC	4248d 14h	/mod_sim_exp/trunk/rtl/
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4248d 15h	/mod_sim_exp/trunk/rtl/
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4248d 15h	/mod_sim_exp/trunk/rtl/
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4248d 17h	/mod_sim_exp/trunk/rtl/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4249d 07h	/mod_sim_exp/trunk/rtl/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4253d 13h	/mod_sim_exp/trunk/rtl/

Browse

Tools

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.0/] [rtl/] - Rev 104

Filtering Options