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[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] [vhdl/] - Rev 98

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80 renamed to version 1.1 to follow the versioning system JonasDC 4096d 17h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.		 JonasDC 4136d 18h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4204d 23h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4208d 16h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
43 made the core parameters generics JonasDC 4208d 16h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4215d 00h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
41 removed deprecated files from version control JonasDC 4215d 00h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
40 adjusted core instantiation to new core module name JonasDC 4223d 04h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4223d 15h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4223d 21h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4227d 18h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4228d 14h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4228d 18h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4228d 21h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4228d 21h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4229d 03h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4229d 03h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4229d 17h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4233d 02h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
23 added descriptive comments JonasDC 4233d 03h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4235d 21h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
21 changed x_i signal to xi JonasDC 4237d 04h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4237d 05h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic		 JonasDC 4242d 00h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
18 updated stages with comments and renamed some signals for consistency JonasDC 4242d 23h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4243d 04h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
16 package with modified generic parameter for register_n JonasDC 4243d 17h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
15 changed generic for register width from n to width for consistency JonasDC 4243d 17h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
14 changed comments, file is now according to OC design rules JonasDC 4243d 18h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules		 JonasDC 4243d 18h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/

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