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[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] - Rev 65

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Rev Log message Author Age Path
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package		 JonasDC 4152d 22h /mod_sim_exp/tags/Release_1.3/rtl/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4153d 03h /mod_sim_exp/tags/Release_1.3/rtl/
62 not used anymore JonasDC 4153d 06h /mod_sim_exp/tags/Release_1.3/rtl/
61 updated comments, added optional altera constraint JonasDC 4153d 06h /mod_sim_exp/tags/Release_1.3/rtl/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.		 JonasDC 4155d 20h /mod_sim_exp/tags/Release_1.3/rtl/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)		 JonasDC 4155d 21h /mod_sim_exp/tags/Release_1.3/rtl/
55 updated resource usage in comments JonasDC 4159d 20h /mod_sim_exp/tags/Release_1.3/rtl/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4159d 20h /mod_sim_exp/tags/Release_1.3/rtl/
53 correctly inferred ram for altera dual port ram JonasDC 4160d 03h /mod_sim_exp/tags/Release_1.3/rtl/
52 correct inferring of blockram, no additional resources. JonasDC 4160d 03h /mod_sim_exp/tags/Release_1.3/rtl/
51 true dual port ram for xilinx JonasDC 4160d 04h /mod_sim_exp/tags/Release_1.3/rtl/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 4160d 04h /mod_sim_exp/tags/Release_1.3/rtl/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4240d 04h /mod_sim_exp/tags/Release_1.3/rtl/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4243d 21h /mod_sim_exp/tags/Release_1.3/rtl/
43 made the core parameters generics JonasDC 4243d 21h /mod_sim_exp/tags/Release_1.3/rtl/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4250d 05h /mod_sim_exp/tags/Release_1.3/rtl/
41 removed deprecated files from version control JonasDC 4250d 05h /mod_sim_exp/tags/Release_1.3/rtl/
40 adjusted core instantiation to new core module name JonasDC 4258d 09h /mod_sim_exp/tags/Release_1.3/rtl/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4258d 20h /mod_sim_exp/tags/Release_1.3/rtl/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4259d 02h /mod_sim_exp/tags/Release_1.3/rtl/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4262d 23h /mod_sim_exp/tags/Release_1.3/rtl/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4263d 19h /mod_sim_exp/tags/Release_1.3/rtl/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4263d 23h /mod_sim_exp/tags/Release_1.3/rtl/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4264d 02h /mod_sim_exp/tags/Release_1.3/rtl/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4264d 03h /mod_sim_exp/tags/Release_1.3/rtl/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4264d 08h /mod_sim_exp/tags/Release_1.3/rtl/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4264d 08h /mod_sim_exp/tags/Release_1.3/rtl/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4264d 22h /mod_sim_exp/tags/Release_1.3/rtl/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4268d 07h /mod_sim_exp/tags/Release_1.3/rtl/
23 added descriptive comments JonasDC 4268d 08h /mod_sim_exp/tags/Release_1.3/rtl/

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