URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] [vhdl/] - Rev 36

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Rev	Log message	Author	Age	Path
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4264d 11h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4264d 15h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4264d 18h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4264d 19h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4265d 00h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4265d 00h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4265d 14h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4268d 23h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
23	added descriptive comments	JonasDC	4269d 00h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4271d 18h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
21	changed x_i signal to xi	JonasDC	4273d 01h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4273d 02h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4277d 21h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4278d 20h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4279d 01h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
16	package with modified generic parameter for register_n	JonasDC	4279d 15h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
15	changed generic for register width from n to width for consistency	JonasDC	4279d 15h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
14	changed comments, file is now according to OC design rules	JonasDC	4279d 15h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4279d 15h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
12	updated comments, file is now completely according to design rules	JonasDC	4279d 15h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
10	changed signal input port names to correct name	JonasDC	4279d 20h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4279d 20h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
8	added descriptive comments	JonasDC	4279d 22h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4279d 23h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4279d 23h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4280d 01h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4280d 15h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4284d 21h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/

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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] [vhdl/] - Rev 36

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