| Rev |
Log message |
Author |
Age |
Path |
| 67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4145d 18h |
/mod_sim_exp/tags/Release_1.4/ |
| 66 |
added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools. |
JonasDC |
4145d 18h |
/mod_sim_exp/tags/Release_1.4/ |
| 65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4153d 10h |
/mod_sim_exp/tags/Release_1.4/ |
| 64 |
added synthesis reports of xilinx and altera |
JonasDC |
4153d 15h |
/mod_sim_exp/tags/Release_1.4/ |
| 63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4153d 15h |
/mod_sim_exp/tags/Release_1.4/ |
| 62 |
not used anymore |
JonasDC |
4153d 18h |
/mod_sim_exp/tags/Release_1.4/ |
| 61 |
updated comments, added optional altera constraint |
JonasDC |
4153d 18h |
/mod_sim_exp/tags/Release_1.4/ |
| 60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4156d 08h |
/mod_sim_exp/tags/Release_1.4/ |
| 59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4156d 09h |
/mod_sim_exp/tags/Release_1.4/ |
| 55 |
updated resource usage in comments |
JonasDC |
4160d 08h |
/mod_sim_exp/tags/Release_1.4/ |
| 54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4160d 08h |
/mod_sim_exp/tags/Release_1.4/ |
| 53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4160d 15h |
/mod_sim_exp/tags/Release_1.4/ |
| 52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4160d 15h |
/mod_sim_exp/tags/Release_1.4/ |
| 51 |
true dual port ram for xilinx |
JonasDC |
4160d 16h |
/mod_sim_exp/tags/Release_1.4/ |
| 50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4160d 16h |
/mod_sim_exp/tags/Release_1.4/ |
| 47 |
added documentation for the IP core. |
JonasDC |
4240d 16h |
/mod_sim_exp/tags/Release_1.4/ |
| 46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4240d 16h |
/mod_sim_exp/tags/Release_1.4/ |
| 45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4240d 16h |
/mod_sim_exp/tags/Release_1.4/ |
| 44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4244d 09h |
/mod_sim_exp/tags/Release_1.4/ |
| 43 |
made the core parameters generics |
JonasDC |
4244d 09h |
/mod_sim_exp/tags/Release_1.4/ |
| 42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4250d 17h |
/mod_sim_exp/tags/Release_1.4/ |
| 41 |
removed deprecated files from version control |
JonasDC |
4250d 17h |
/mod_sim_exp/tags/Release_1.4/ |
| 40 |
adjusted core instantiation to new core module name |
JonasDC |
4258d 21h |
/mod_sim_exp/tags/Release_1.4/ |
| 39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4259d 09h |
/mod_sim_exp/tags/Release_1.4/ |
| 38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4259d 14h |
/mod_sim_exp/tags/Release_1.4/ |
| 37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4263d 11h |
/mod_sim_exp/tags/Release_1.4/ |
| 36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4264d 07h |
/mod_sim_exp/tags/Release_1.4/ |
| 35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4264d 10h |
/mod_sim_exp/tags/Release_1.4/ |
| 34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4264d 11h |
/mod_sim_exp/tags/Release_1.4/ |
| 33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4264d 14h |
/mod_sim_exp/tags/Release_1.4/ |
