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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] - Rev 54

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Rev	Log message	Author	Age	Path
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4228d 11h	/mod_sim_exp/tags/Release_1.4/rtl/
53	correctly inferred ram for altera dual port ram	JonasDC	4228d 18h	/mod_sim_exp/tags/Release_1.4/rtl/
52	correct inferring of blockram, no additional resources.	JonasDC	4228d 18h	/mod_sim_exp/tags/Release_1.4/rtl/
51	true dual port ram for xilinx	JonasDC	4228d 19h	/mod_sim_exp/tags/Release_1.4/rtl/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4228d 19h	/mod_sim_exp/tags/Release_1.4/rtl/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4308d 19h	/mod_sim_exp/tags/Release_1.4/rtl/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4312d 12h	/mod_sim_exp/tags/Release_1.4/rtl/
43	made the core parameters generics	JonasDC	4312d 12h	/mod_sim_exp/tags/Release_1.4/rtl/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4318d 20h	/mod_sim_exp/tags/Release_1.4/rtl/
41	removed deprecated files from version control	JonasDC	4318d 20h	/mod_sim_exp/tags/Release_1.4/rtl/
40	adjusted core instantiation to new core module name	JonasDC	4327d 00h	/mod_sim_exp/tags/Release_1.4/rtl/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4327d 11h	/mod_sim_exp/tags/Release_1.4/rtl/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4327d 17h	/mod_sim_exp/tags/Release_1.4/rtl/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4331d 14h	/mod_sim_exp/tags/Release_1.4/rtl/
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4332d 10h	/mod_sim_exp/tags/Release_1.4/rtl/
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4332d 14h	/mod_sim_exp/tags/Release_1.4/rtl/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4332d 17h	/mod_sim_exp/tags/Release_1.4/rtl/
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4332d 18h	/mod_sim_exp/tags/Release_1.4/rtl/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4332d 23h	/mod_sim_exp/tags/Release_1.4/rtl/
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4332d 23h	/mod_sim_exp/tags/Release_1.4/rtl/
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4333d 13h	/mod_sim_exp/tags/Release_1.4/rtl/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4336d 22h	/mod_sim_exp/tags/Release_1.4/rtl/
23	added descriptive comments	JonasDC	4336d 23h	/mod_sim_exp/tags/Release_1.4/rtl/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4339d 17h	/mod_sim_exp/tags/Release_1.4/rtl/
21	changed x_i signal to xi	JonasDC	4341d 00h	/mod_sim_exp/tags/Release_1.4/rtl/
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4341d 01h	/mod_sim_exp/tags/Release_1.4/rtl/
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4345d 20h	/mod_sim_exp/tags/Release_1.4/rtl/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4346d 19h	/mod_sim_exp/tags/Release_1.4/rtl/
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4347d 00h	/mod_sim_exp/tags/Release_1.4/rtl/
16	package with modified generic parameter for register_n	JonasDC	4347d 13h	/mod_sim_exp/tags/Release_1.4/rtl/

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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] - Rev 54

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