| Rev |
Log message |
Author |
Age |
Path |
| 67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4133d 08h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 66 |
added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools. |
JonasDC |
4133d 08h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4141d 00h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4141d 06h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 62 |
not used anymore |
JonasDC |
4141d 09h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 61 |
updated comments, added optional altera constraint |
JonasDC |
4141d 09h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4143d 23h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4143d 23h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 55 |
updated resource usage in comments |
JonasDC |
4147d 23h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4147d 23h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4148d 06h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4148d 06h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 51 |
true dual port ram for xilinx |
JonasDC |
4148d 07h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4148d 07h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4228d 07h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4232d 00h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 43 |
made the core parameters generics |
JonasDC |
4232d 00h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4238d 08h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 41 |
removed deprecated files from version control |
JonasDC |
4238d 08h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 40 |
adjusted core instantiation to new core module name |
JonasDC |
4246d 12h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4246d 23h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4247d 05h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4251d 02h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4251d 22h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4252d 02h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4252d 04h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4252d 05h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4252d 11h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4252d 11h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4253d 01h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
