Rev |
Log message |
Author |
Age |
Path |
226 |
Forgot the updated package file... |
jshamlet |
1560d 03h |
/open8_urisc/ |
225 |
Added Halt_Ack to go with Halt_Req. |
jshamlet |
1560d 03h |
/open8_urisc/ |
224 |
Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. |
jshamlet |
1560d 05h |
/open8_urisc/ |
223 |
Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. |
jshamlet |
1560d 22h |
/open8_urisc/ |
222 |
Created a modified version of the epoch timer with a 32-bit, 1-uS resolution timer/comparator. |
jshamlet |
1561d 03h |
/open8_urisc/ |
221 |
o8_vdsm8.vhd now has a default value assigned at compile time, o8_register.vhd was cleaned up some more. |
jshamlet |
1561d 22h |
/open8_urisc/ |
220 |
More revision sections added |
jshamlet |
1561d 22h |
/open8_urisc/ |
219 |
Added revision block and corrected creation date. |
jshamlet |
1561d 22h |
/open8_urisc/ |
218 |
Revision sections added,
vdsm8.vhd added. |
jshamlet |
1561d 22h |
/open8_urisc/ |
217 |
Broke out the vdsm8 as a separate entity, since it is used in several places,
Even MORE code cleanup. |
jshamlet |
1561d 22h |
/open8_urisc/ |
216 |
Fixed missing parenthesis |
jshamlet |
1562d 01h |
/open8_urisc/ |
215 |
More code cleanup |
jshamlet |
1562d 01h |
/open8_urisc/ |
214 |
Initial add of some older code |
jshamlet |
1565d 23h |
/open8_urisc/ |
213 |
Code and comment cleanup |
jshamlet |
1565d 23h |
/open8_urisc/ |
212 |
Fixed issue with rewritten epoch timer not clearing alarm on set point write. |
jshamlet |
1566d 05h |
/open8_urisc/ |
211 |
Ok, this time with feeling. Timer should now properly reset on interval update. |
jshamlet |
1567d 03h |
/open8_urisc/ |
210 |
Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes. |
jshamlet |
1567d 05h |
/open8_urisc/ |
209 |
Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core. |
jshamlet |
1567d 18h |
/open8_urisc/ |
208 |
Removed unnecessary package references |
jshamlet |
1568d 03h |
/open8_urisc/ |
207 |
Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. |
jshamlet |
1568d 21h |
/open8_urisc/ |
206 |
Merged interrupt logic with other clocked process. |
jshamlet |
1572d 15h |
/open8_urisc/ |
205 |
More code and comment cleanup for the new SDLC engine |
jshamlet |
1572d 16h |
/open8_urisc/ |
204 |
Fixed more incorrect comments |
jshamlet |
1572d 16h |
/open8_urisc/ |
203 |
Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. |
jshamlet |
1572d 22h |
/open8_urisc/ |
202 |
Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier. |
jshamlet |
1572d 23h |
/open8_urisc/ |
201 |
Fixed comments regarding RX Checksum location |
jshamlet |
1574d 20h |
/open8_urisc/ |
200 |
Renamed dual-port buffer to match other entities. |
jshamlet |
1574d 20h |
/open8_urisc/ |
199 |
Added monitor ram for debugging and fixed issue with dual-port read path. |
jshamlet |
1574d 21h |
/open8_urisc/ |
198 |
Removed debugging memory |
jshamlet |
1575d 05h |
/open8_urisc/ |
197 |
Fixed incorrect comments |
jshamlet |
1575d 05h |
/open8_urisc/ |