| Rev |
Log message |
Author |
Age |
Path |
| 275 |
Fixed a minor comment error. |
jshamlet |
1327d 08h |
/open8_urisc/ |
| 274 |
Updated comments with more corrections |
jshamlet |
1327d 15h |
/open8_urisc/ |
| 273 |
Updated comments with corrections |
jshamlet |
1327d 17h |
/open8_urisc/ |
| 272 |
Updated the HTML documentation to reflect the removed generic. |
jshamlet |
1337d 16h |
/open8_urisc/ |
| 271 |
Removed deleted generic define. |
jshamlet |
1337d 16h |
/open8_urisc/ |
| 270 |
Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.
Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU. |
jshamlet |
1337d 16h |
/open8_urisc/ |
| 269 |
Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance. |
jshamlet |
1340d 06h |
/open8_urisc/ |
| 268 |
Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. |
jshamlet |
1340d 07h |
/open8_urisc/ |
| 267 |
Corrected the file description to indicate this is an example package. |
jshamlet |
1340d 07h |
/open8_urisc/ |
| 266 |
Accidentally uploaded incorrect example file for Open8_cfg.vhd |
jshamlet |
1340d 07h |
/open8_urisc/ |
| 265 |
Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset. |
jshamlet |
1432d 15h |
/open8_urisc/ |
| 264 |
Updated comments |
jshamlet |
1442d 13h |
/open8_urisc/ |
| 263 |
Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.
Also separated the SDLC TX and RX interrupts so that they could be handled separately. |
jshamlet |
1442d 13h |
/open8_urisc/ |
| 262 |
Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map. |
jshamlet |
1451d 16h |
/open8_urisc/ |
| 261 |
Increased delay timer to 7 bits for button press detection. |
jshamlet |
1458d 16h |
/open8_urisc/ |
| 260 |
Added missing comments for Sequential_Interrupts generic, as well as comments explaining portions of the CPU operations. |
jshamlet |
1471d 15h |
/open8_urisc/ |
| 259 |
Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect was set to FALSE,
Added a pulse interval measurement entity,
Fixed comments. |
jshamlet |
1471d 17h |
/open8_urisc/ |
| 258 |
Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and the sys_tick.vhd utility entity. |
jshamlet |
1472d 15h |
/open8_urisc/ |
| 257 |
Fixed misnamed signal in o8_7seg.vhd and added a replacement switch interface that handles both static and pushbutton switches. |
jshamlet |
1472d 15h |
/open8_urisc/ |
| 256 |
Removed unused generic from the status_led.vhd and cleaned up comments on the CPU |
jshamlet |
1472d 16h |
/open8_urisc/ |
| 255 |
Modified code to make ModelSim happy (It didn't like the generate blocks for some reason). Also added a block describing the new generic. |
jshamlet |
1472d 21h |
/open8_urisc/ |
| 254 |
Simplified the ISR address logic so that the upper 12 bits are constant (set by generic) and only the lower 4 bits are registered/computed. |
jshamlet |
1473d 11h |
/open8_urisc/ |
| 253 |
Fixed spelling error in comment |
jshamlet |
1473d 12h |
/open8_urisc/ |
| 252 |
(This time the CPU model was included...)
Added the ability to use unsigned offsets to the LDO/STO instructions. The original behavior of signed offsets is preserved if the Unsigned_Index_Offsets is left unset or set to FALSE. While inserting this code, pipeline registers were also inserted into the address generation logic for indexed instructions. This simplifies the final multiplexor and improves FMax at the slight expense of LDO/SDO now taking one additional clock cycle to execute. |
jshamlet |
1473d 12h |
/open8_urisc/ |
| 251 |
Added RAM write fault detection, which can be used to indicate a memory write violation by the CPU. This allows a clean shutdown in the event of a memory problem/program crash.
Fixed a bug in the status_led.vhd entity that kept the flashing light function from working. The new code uses a maximal length 24-bit LFSR to create long delays. This is more efficient than a binary counter, but results in non-exact frequencies as a function of SYSTEM_FREQUENCY / (2^24-1).
Added the ability to use unsigned offsets to the LDO/STO instructions. The original behavior of signed offsets is preserved if the Unsigned_Index_Offsets is left unset or set to FALSE. While inserting this code, pipeline registers were also inserted into the address generation logic for indexed instructions. This simplifies the final multiplexor and improves FMax at the slight expense of LDO/SDO now taking one additional clock cycle to execute. |
jshamlet |
1473d 12h |
/open8_urisc/ |
| 250 |
Removed monitor RAM from SDLC model, as it is now proven to work. |
jshamlet |
1477d 20h |
/open8_urisc/ |
| 249 |
Added a 32-bit wide register and split the status_led core from o8_status_led.vhd, allowing it to be used as a subcomponent elsewhere. |
jshamlet |
1489d 12h |
/open8_urisc/ |
| 248 |
Removed Default_Int_Flag generic from CPU, as it is duplicated by Supervisor_Mode. |
jshamlet |
1489d 20h |
/open8_urisc/ |
| 247 |
Fixed problem where parallel interface was always forcing the data registers due to bad alias. |
jshamlet |
1490d 13h |
/open8_urisc/ |
| 246 |
The system timer module now allows for an optional millisecond resolution (settable through a generic). This prescalar enable permits the timer to operate from 1 to 256 mS, which is useful for a variety of tasks, such as serial timeouts and watchdog timers. The enable is not software settable, as this would complicate the register interface and isn't generally useful in an HDL based SOC design.
The vector interface now has a parallel interface that runs beside the serial interface, and is useful for connecting to DIO cards or other parallel interfaces. |
jshamlet |
1490d 18h |
/open8_urisc/ |
