| Rev |
Log message |
Author |
Age |
Path |
| 281 |
Added pre-initialization to the dual-port RAM signals. |
jshamlet |
1288d 23h |
/open8_urisc/ |
| 280 |
Got rid of silly aliases that connected the dual-port memory and the arbitration logic. |
jshamlet |
1288d 23h |
/open8_urisc/ |
| 279 |
More comment cleanup |
jshamlet |
1289d 20h |
/open8_urisc/ |
| 278 |
Flattened the SDLC interface to fewer files and eliminated the package file. |
jshamlet |
1290d 14h |
/open8_urisc/ |
| 277 |
Fixed documentation errors related to flags. The UPP ALU instruction only alters the C flag, not the Z or N flags. This implies that using indexed loads or stores with auto post-increment will potentially alter the C flag. |
jshamlet |
1290d 20h |
/open8_urisc/ |
| 276 |
More comment fixes |
jshamlet |
1325d 17h |
/open8_urisc/ |
| 275 |
Fixed a minor comment error. |
jshamlet |
1327d 11h |
/open8_urisc/ |
| 274 |
Updated comments with more corrections |
jshamlet |
1327d 18h |
/open8_urisc/ |
| 273 |
Updated comments with corrections |
jshamlet |
1327d 20h |
/open8_urisc/ |
| 272 |
Updated the HTML documentation to reflect the removed generic. |
jshamlet |
1337d 19h |
/open8_urisc/ |
| 271 |
Removed deleted generic define. |
jshamlet |
1337d 19h |
/open8_urisc/ |
| 270 |
Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.
Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU. |
jshamlet |
1337d 19h |
/open8_urisc/ |
| 269 |
Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance. |
jshamlet |
1340d 09h |
/open8_urisc/ |
| 268 |
Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. |
jshamlet |
1340d 09h |
/open8_urisc/ |
| 267 |
Corrected the file description to indicate this is an example package. |
jshamlet |
1340d 09h |
/open8_urisc/ |
| 266 |
Accidentally uploaded incorrect example file for Open8_cfg.vhd |
jshamlet |
1340d 10h |
/open8_urisc/ |
| 265 |
Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset. |
jshamlet |
1432d 18h |
/open8_urisc/ |
| 264 |
Updated comments |
jshamlet |
1442d 15h |
/open8_urisc/ |
| 263 |
Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.
Also separated the SDLC TX and RX interrupts so that they could be handled separately. |
jshamlet |
1442d 16h |
/open8_urisc/ |
| 262 |
Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map. |
jshamlet |
1451d 19h |
/open8_urisc/ |
| 261 |
Increased delay timer to 7 bits for button press detection. |
jshamlet |
1458d 19h |
/open8_urisc/ |
| 260 |
Added missing comments for Sequential_Interrupts generic, as well as comments explaining portions of the CPU operations. |
jshamlet |
1471d 18h |
/open8_urisc/ |
| 259 |
Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect was set to FALSE,
Added a pulse interval measurement entity,
Fixed comments. |
jshamlet |
1471d 20h |
/open8_urisc/ |
| 258 |
Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and the sys_tick.vhd utility entity. |
jshamlet |
1472d 17h |
/open8_urisc/ |
| 257 |
Fixed misnamed signal in o8_7seg.vhd and added a replacement switch interface that handles both static and pushbutton switches. |
jshamlet |
1472d 18h |
/open8_urisc/ |
| 256 |
Removed unused generic from the status_led.vhd and cleaned up comments on the CPU |
jshamlet |
1472d 19h |
/open8_urisc/ |
| 255 |
Modified code to make ModelSim happy (It didn't like the generate blocks for some reason). Also added a block describing the new generic. |
jshamlet |
1473d 00h |
/open8_urisc/ |
| 254 |
Simplified the ISR address logic so that the upper 12 bits are constant (set by generic) and only the lower 4 bits are registered/computed. |
jshamlet |
1473d 14h |
/open8_urisc/ |
| 253 |
Fixed spelling error in comment |
jshamlet |
1473d 15h |
/open8_urisc/ |
| 252 |
(This time the CPU model was included...)
Added the ability to use unsigned offsets to the LDO/STO instructions. The original behavior of signed offsets is preserved if the Unsigned_Index_Offsets is left unset or set to FALSE. While inserting this code, pipeline registers were also inserted into the address generation logic for indexed instructions. This simplifies the final multiplexor and improves FMax at the slight expense of LDO/SDO now taking one additional clock cycle to execute. |
jshamlet |
1473d 15h |
/open8_urisc/ |
