Rev |
Log message |
Author |
Age |
Path |
186 |
Merged the interrupt override logic into the case structure, simplifying how interrupts are processed. |
jshamlet |
1635d 03h |
/open8_urisc/trunk/ |
185 |
1) Fixed an apparently long-standing bug where the interrupt bit wasn't being cleared after an RTI
2) Modified the program counter logic to be simpler. It now always increments, and states control the increment using the offset field. A new set of constants was added to replace the old states.
3) Modified the ALU to always use Operand1 instead of ALU_Ctrl.Data (and removed the field in the record). A new ALU command, ALU_GMSK, was added, as it was the only instruction to set the .Data field to something other than Operand1 (Int_Mask)
4) Modified the package file so that flag names match what the assembler calls them. FL_Z is now PSR_Z, FL_GP1 is now PSR_GP4, etc.
5) Cleaned up the comments and code formatting |
jshamlet |
1635d 06h |
/open8_urisc/trunk/ |
184 |
More file/entity renaming to match private versions. |
jshamlet |
1637d 06h |
/open8_urisc/trunk/ |
183 |
Renamed core to o8_cpu to match new naming scheme |
jshamlet |
1637d 06h |
/open8_urisc/trunk/ |
182 |
Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. |
jshamlet |
1637d 06h |
/open8_urisc/trunk/ |
181 |
Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. |
jshamlet |
1638d 03h |
/open8_urisc/trunk/ |
180 |
Added additional Open8 compatible modules |
jshamlet |
1642d 06h |
/open8_urisc/trunk/ |
179 |
Replacing files accidentally deleted during check-in |
jshamlet |
1652d 02h |
/open8_urisc/trunk/ |
178 |
Adding Open8 toolset for pure assembly |
jshamlet |
1652d 02h |
/open8_urisc/trunk/ |
177 |
Fixed comments in RTC module |
jshamlet |
2962d 07h |
/open8_urisc/trunk/ |
176 |
Fixed documentation errors,
Modified uSec_Tick such that it is always generated regardless of the interval. |
jshamlet |
2967d 04h |
/open8_urisc/trunk/ |
175 |
Added 4 and 8-bit LCD interfaces with backlight and contrast DACs |
jshamlet |
2967d 09h |
/open8_urisc/trunk/ |
174 |
Added ROM/RAM wrappers |
jshamlet |
3162d 04h |
/open8_urisc/trunk/ |
173 |
Added a couple of useful interfaces for detecting button presses and clock changes. |
jshamlet |
3162d 04h |
/open8_urisc/trunk/ |
172 |
General code cleanup |
jshamlet |
3162d 04h |
/open8_urisc/trunk/ |
171 |
Fixed comments for offsets 0x0 - 0x3 to indicate the read value |
jshamlet |
3162d 04h |
/open8_urisc/trunk/ |
170 |
Added 24-bit resolution epoch timer / alarm clock |
jshamlet |
3162d 04h |
/open8_urisc/trunk/ |
169 |
Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. |
jshamlet |
3217d 05h |
/open8_urisc/trunk/ |
168 |
Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component, |
jshamlet |
3996d 01h |
/open8_urisc/trunk/ |
167 |
Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus. |
jshamlet |
4003d 23h |
/open8_urisc/trunk/ |
166 |
fixed additional issues with range checking on PCREL relocations for open8, added test cases to verify, catch tree up with binutils datestamp 20120301 |
khays |
4568d 01h |
/open8_urisc/trunk/ |
165 |
fixed issues with PC relative fixups in the linker |
khays |
4569d 08h |
/open8_urisc/trunk/ |
164 |
Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. |
jshamlet |
4639d 19h |
/open8_urisc/trunk/ |
163 |
sync with binutils 2.22.51.20111114 |
khays |
4677d 07h |
/open8_urisc/trunk/ |
162 |
Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. |
jshamlet |
4730d 12h |
/open8_urisc/trunk/ |
161 |
synchronize binutils/ with gnu dev tree of 2.21.53.20110828 |
khays |
4754d 07h |
/open8_urisc/trunk/ |
160 |
synchronize binutils/gas with gnu dev tree of 2.21.53.20110828 |
khays |
4754d 07h |
/open8_urisc/trunk/ |
159 |
synchronize binutils/gold with gnu dev tree of 2.21.53.20110828 |
khays |
4754d 07h |
/open8_urisc/trunk/ |
158 |
synchronize binutils/opcodes with gnu dev tree of 2.21.53.20110828 |
khays |
4754d 07h |
/open8_urisc/trunk/ |
157 |
synchronize binutils/ld with gnu dev tree of 2.21.53.20110828 |
khays |
4754d 07h |
/open8_urisc/trunk/ |