OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] - Rev 295

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
295 Undoing previous revision. UART was fine, bug reporter was not. jshamlet 1012d 00h /open8_urisc/trunk/
294 Fixed an ancient bug in the parity logic that had the parity inverted. jshamlet 1012d 04h /open8_urisc/trunk/
293 Fixed formatting issue in o8_sync_serial where tabs were inserted instead of spaces and fixed column spacing as a result (purely cosmetic) jshamlet 1031d 04h /open8_urisc/trunk/
292 Updated the o8_trig_delay entity by:
1) Added a global interrupt enable,
2) Added the ability to trigger on both the pre- and post-arm trigger input
3) Added the ability to read the external input on offset 7
jshamlet 1102d 04h /open8_urisc/trunk/
291 Added Notepad++ language definition file for the Open8_II ISA jshamlet 1144d 18h /open8_urisc/trunk/
290 Added an additional generic "Rotation_Ignores_Carry" that removes the carry logic from the ROL/ROR instructions such that they now rotate 'normally',
Added an alias for PSR_GP4 named PSR_S, as it is now used to switch the function of the RSP instruction. The internal opcode hasn't changed, but it allows assembly code to use PSR_S or BRS/BNS when performing RSP related operations.
jshamlet 1144d 18h /open8_urisc/trunk/
289 Added back the delay for the cursor home command, since it is slow on most Hitachi compatible LCD panels. jshamlet 1162d 05h /open8_urisc/trunk/
288 Removed hard-wired R/Wn output and replaced it with a note that the R/Wn line must be tied low either in firmware or on the board. jshamlet 1163d 01h /open8_urisc/trunk/
287 Fixed mangled comments and revisioning dates. jshamlet 1164d 00h /open8_urisc/trunk/
286 Added initial cut of a "universal" character LCD driver. Allows for adjustment of address setup, enable high, and cycle times. Also has built-in timers for handling timing on certain commands. jshamlet 1164d 01h /open8_urisc/trunk/
285 Added checksum byte to vector tx/rx to avoid issues with serial line noise glitching the receiver. Also modified the transmitted to take any generic argument, rather than canned arguments. jshamlet 1171d 04h /open8_urisc/trunk/
284 Corrected the vhdl unit name and description for o8_7seg.vhd jshamlet 1284d 15h /open8_urisc/trunk/
283 Altered SDLC bitclock check on TX to NOT block when tested by software, but to instead ignore packet write requests if BClk_Okay is low. This allows software to continue checking BClk_Okay in a polling loop. jshamlet 1288d 02h /open8_urisc/trunk/
282 Modified the SDLC core transmit states to have consistent naming. jshamlet 1288d 03h /open8_urisc/trunk/
281 Added pre-initialization to the dual-port RAM signals. jshamlet 1288d 06h /open8_urisc/trunk/
280 Got rid of silly aliases that connected the dual-port memory and the arbitration logic. jshamlet 1288d 06h /open8_urisc/trunk/
279 More comment cleanup jshamlet 1289d 03h /open8_urisc/trunk/
278 Flattened the SDLC interface to fewer files and eliminated the package file. jshamlet 1289d 21h /open8_urisc/trunk/
277 Fixed documentation errors related to flags. The UPP ALU instruction only alters the C flag, not the Z or N flags. This implies that using indexed loads or stores with auto post-increment will potentially alter the C flag. jshamlet 1290d 03h /open8_urisc/trunk/
276 More comment fixes jshamlet 1325d 00h /open8_urisc/trunk/
275 Fixed a minor comment error. jshamlet 1326d 18h /open8_urisc/trunk/
274 Updated comments with more corrections jshamlet 1327d 01h /open8_urisc/trunk/
273 Updated comments with corrections jshamlet 1327d 02h /open8_urisc/trunk/
272 Updated the HTML documentation to reflect the removed generic. jshamlet 1337d 02h /open8_urisc/trunk/
271 Removed deleted generic define. jshamlet 1337d 02h /open8_urisc/trunk/
270 Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.

Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.
jshamlet 1337d 02h /open8_urisc/trunk/
269 Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance. jshamlet 1339d 15h /open8_urisc/trunk/
268 Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. jshamlet 1339d 16h /open8_urisc/trunk/
267 Corrected the file description to indicate this is an example package. jshamlet 1339d 16h /open8_urisc/trunk/
266 Accidentally uploaded incorrect example file for Open8_cfg.vhd jshamlet 1339d 16h /open8_urisc/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.