| Rev |
Log message |
Author |
Age |
Path |
| 212 |
Fixed issue with rewritten epoch timer not clearing alarm on set point write. |
jshamlet |
1537d 23h |
/open8_urisc/trunk/VHDL/ |
| 211 |
Ok, this time with feeling. Timer should now properly reset on interval update. |
jshamlet |
1538d 20h |
/open8_urisc/trunk/VHDL/ |
| 210 |
Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes. |
jshamlet |
1538d 23h |
/open8_urisc/trunk/VHDL/ |
| 209 |
Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core. |
jshamlet |
1539d 12h |
/open8_urisc/trunk/VHDL/ |
| 208 |
Removed unnecessary package references |
jshamlet |
1539d 21h |
/open8_urisc/trunk/VHDL/ |
| 207 |
Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. |
jshamlet |
1540d 14h |
/open8_urisc/trunk/VHDL/ |
| 206 |
Merged interrupt logic with other clocked process. |
jshamlet |
1544d 09h |
/open8_urisc/trunk/VHDL/ |
| 205 |
More code and comment cleanup for the new SDLC engine |
jshamlet |
1544d 09h |
/open8_urisc/trunk/VHDL/ |
| 204 |
Fixed more incorrect comments |
jshamlet |
1544d 09h |
/open8_urisc/trunk/VHDL/ |
| 203 |
Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. |
jshamlet |
1544d 16h |
/open8_urisc/trunk/VHDL/ |
| 202 |
Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier. |
jshamlet |
1544d 16h |
/open8_urisc/trunk/VHDL/ |
| 201 |
Fixed comments regarding RX Checksum location |
jshamlet |
1546d 14h |
/open8_urisc/trunk/VHDL/ |
| 200 |
Renamed dual-port buffer to match other entities. |
jshamlet |
1546d 14h |
/open8_urisc/trunk/VHDL/ |
| 199 |
Added monitor ram for debugging and fixed issue with dual-port read path. |
jshamlet |
1546d 14h |
/open8_urisc/trunk/VHDL/ |
| 198 |
Removed debugging memory |
jshamlet |
1546d 22h |
/open8_urisc/trunk/VHDL/ |
| 197 |
Fixed incorrect comments |
jshamlet |
1546d 22h |
/open8_urisc/trunk/VHDL/ |
| 196 |
Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) |
jshamlet |
1546d 23h |
/open8_urisc/trunk/VHDL/ |
| 195 |
Added dual-port RAM core for SDLC interface. |
jshamlet |
1547d 17h |
/open8_urisc/trunk/VHDL/ |
| 194 |
Cleaned up licensing sections |
jshamlet |
1547d 17h |
/open8_urisc/trunk/VHDL/ |
| 193 |
Fixed incorrect comment in o8_alu16.vhd. The value of the write to 0x1F doesn't matter, as the write itself triggers the calculation. |
jshamlet |
1547d 18h |
/open8_urisc/trunk/VHDL/ |
| 192 |
Added SDLC packet engine |
jshamlet |
1547d 18h |
/open8_urisc/trunk/VHDL/ |
| 191 |
Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it. |
jshamlet |
1547d 18h |
/open8_urisc/trunk/VHDL/ |
| 190 |
Fixed a bug in CPU where RTI/RTS wasn't idling the instruction cache, causing intermittent failures where RTI would execute as RTS, corrupting the stack;
Fixed a bug in the real-time clock where the uSec tick generator would stop if the PIT timer value was left/set to 0x00. |
jshamlet |
1559d 16h |
/open8_urisc/trunk/VHDL/ |
| 189 |
Merged changes from private repository,
added ceil_log2 function to Open8_pkg, since it is used to calculate RAM vectors,
cleaned up comments and removed local copies of the ceil_log2 function from peripherals. |
jshamlet |
1560d 16h |
/open8_urisc/trunk/VHDL/ |
| 188 |
Added a generic to alter the behavior of RTI so that it can optionally skip restoring the general purpose flags GP4 to GP7, allowing ISR's to make persistent changes to them. Also exported these flags to the top level for use outside the CPU. |
jshamlet |
1560d 19h |
/open8_urisc/trunk/VHDL/ |
| 187 |
Added the CPU_Halt input, only now as an input to the instruction decoder. The CPU_Halt line will assert the registered CPU_Halt_Req, which will cause the instruction decoder to abort the current instruction, reset the PC, then enter a hold state until the line is deasserted. Additionally, a very minor bug that could cause the SMSK instruction to effectively execute twice if interrupted was fixed. Lastly, cleaned up the comments even more. |
jshamlet |
1562d 15h |
/open8_urisc/trunk/VHDL/ |
| 186 |
Merged the interrupt override logic into the case structure, simplifying how interrupts are processed. |
jshamlet |
1565d 15h |
/open8_urisc/trunk/VHDL/ |
| 185 |
1) Fixed an apparently long-standing bug where the interrupt bit wasn't being cleared after an RTI
2) Modified the program counter logic to be simpler. It now always increments, and states control the increment using the offset field. A new set of constants was added to replace the old states.
3) Modified the ALU to always use Operand1 instead of ALU_Ctrl.Data (and removed the field in the record). A new ALU command, ALU_GMSK, was added, as it was the only instruction to set the .Data field to something other than Operand1 (Int_Mask)
4) Modified the package file so that flag names match what the assembler calls them. FL_Z is now PSR_Z, FL_GP1 is now PSR_GP4, etc.
5) Cleaned up the comments and code formatting |
jshamlet |
1565d 18h |
/open8_urisc/trunk/VHDL/ |
| 184 |
More file/entity renaming to match private versions. |
jshamlet |
1567d 18h |
/open8_urisc/trunk/VHDL/ |
| 183 |
Renamed core to o8_cpu to match new naming scheme |
jshamlet |
1567d 18h |
/open8_urisc/trunk/VHDL/ |
