| Rev |
Log message |
Author |
Age |
Path |
| 219 |
Added revision block and corrected creation date. |
jshamlet |
1517d 20h |
/open8_urisc/trunk/VHDL/ |
| 218 |
Revision sections added,
vdsm8.vhd added. |
jshamlet |
1517d 20h |
/open8_urisc/trunk/VHDL/ |
| 217 |
Broke out the vdsm8 as a separate entity, since it is used in several places,
Even MORE code cleanup. |
jshamlet |
1517d 20h |
/open8_urisc/trunk/VHDL/ |
| 216 |
Fixed missing parenthesis |
jshamlet |
1517d 22h |
/open8_urisc/trunk/VHDL/ |
| 215 |
More code cleanup |
jshamlet |
1517d 22h |
/open8_urisc/trunk/VHDL/ |
| 214 |
Initial add of some older code |
jshamlet |
1521d 21h |
/open8_urisc/trunk/VHDL/ |
| 213 |
Code and comment cleanup |
jshamlet |
1521d 21h |
/open8_urisc/trunk/VHDL/ |
| 212 |
Fixed issue with rewritten epoch timer not clearing alarm on set point write. |
jshamlet |
1522d 03h |
/open8_urisc/trunk/VHDL/ |
| 211 |
Ok, this time with feeling. Timer should now properly reset on interval update. |
jshamlet |
1523d 01h |
/open8_urisc/trunk/VHDL/ |
| 210 |
Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes. |
jshamlet |
1523d 03h |
/open8_urisc/trunk/VHDL/ |
| 209 |
Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core. |
jshamlet |
1523d 16h |
/open8_urisc/trunk/VHDL/ |
| 208 |
Removed unnecessary package references |
jshamlet |
1524d 01h |
/open8_urisc/trunk/VHDL/ |
| 207 |
Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. |
jshamlet |
1524d 18h |
/open8_urisc/trunk/VHDL/ |
| 206 |
Merged interrupt logic with other clocked process. |
jshamlet |
1528d 13h |
/open8_urisc/trunk/VHDL/ |
| 205 |
More code and comment cleanup for the new SDLC engine |
jshamlet |
1528d 13h |
/open8_urisc/trunk/VHDL/ |
| 204 |
Fixed more incorrect comments |
jshamlet |
1528d 14h |
/open8_urisc/trunk/VHDL/ |
| 203 |
Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. |
jshamlet |
1528d 20h |
/open8_urisc/trunk/VHDL/ |
| 202 |
Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier. |
jshamlet |
1528d 21h |
/open8_urisc/trunk/VHDL/ |
| 201 |
Fixed comments regarding RX Checksum location |
jshamlet |
1530d 18h |
/open8_urisc/trunk/VHDL/ |
| 200 |
Renamed dual-port buffer to match other entities. |
jshamlet |
1530d 18h |
/open8_urisc/trunk/VHDL/ |
| 199 |
Added monitor ram for debugging and fixed issue with dual-port read path. |
jshamlet |
1530d 18h |
/open8_urisc/trunk/VHDL/ |
| 198 |
Removed debugging memory |
jshamlet |
1531d 02h |
/open8_urisc/trunk/VHDL/ |
| 197 |
Fixed incorrect comments |
jshamlet |
1531d 03h |
/open8_urisc/trunk/VHDL/ |
| 196 |
Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) |
jshamlet |
1531d 03h |
/open8_urisc/trunk/VHDL/ |
| 195 |
Added dual-port RAM core for SDLC interface. |
jshamlet |
1531d 22h |
/open8_urisc/trunk/VHDL/ |
| 194 |
Cleaned up licensing sections |
jshamlet |
1531d 22h |
/open8_urisc/trunk/VHDL/ |
| 193 |
Fixed incorrect comment in o8_alu16.vhd. The value of the write to 0x1F doesn't matter, as the write itself triggers the calculation. |
jshamlet |
1531d 22h |
/open8_urisc/trunk/VHDL/ |
| 192 |
Added SDLC packet engine |
jshamlet |
1531d 23h |
/open8_urisc/trunk/VHDL/ |
| 191 |
Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it. |
jshamlet |
1531d 23h |
/open8_urisc/trunk/VHDL/ |
| 190 |
Fixed a bug in CPU where RTI/RTS wasn't idling the instruction cache, causing intermittent failures where RTI would execute as RTS, corrupting the stack;
Fixed a bug in the real-time clock where the uSec tick generator would stop if the PIT timer value was left/set to 0x00. |
jshamlet |
1543d 20h |
/open8_urisc/trunk/VHDL/ |
