Rev |
Log message |
Author |
Age |
Path |
318 |
Added o8_scale_conv.vhd and intdiv.vhd |
jshamlet |
374d 06h |
/open8_urisc/trunk/VHDL/ |
317 |
Altered the reinit signal on teh adc128s022.vhd driver to be optional, and removed the "dead" signal from the upper level o8_de0_nano_adc_if.vhd code. |
jshamlet |
388d 03h |
/open8_urisc/trunk/VHDL/ |
316 |
More code cleanup and comments,
Removed INT_VECTOR_n constants, as they are superfluous. There are no reasonable situations in which the constants would be altered. |
jshamlet |
388d 03h |
/open8_urisc/trunk/VHDL/ |
315 |
Added Terasic DE0 Nano ADC interface and rolling averager. |
jshamlet |
388d 04h |
/open8_urisc/trunk/VHDL/ |
314 |
Code cleanup and added comments |
jshamlet |
388d 05h |
/open8_urisc/trunk/VHDL/ |
313 |
Added all generics to package component |
jshamlet |
388d 06h |
/open8_urisc/trunk/VHDL/ |
312 |
Added o8_timer24.vhd as a more flexible alternative to o8_sys_timer_ii.vhd.
Also cleaned up some comments in the HTML documentation |
jshamlet |
388d 06h |
/open8_urisc/trunk/VHDL/ |
310 |
Added optional DACadv signal to advance the PWM engine using an external signal. This is used to synchronize the DAC with other DACs or for streaming multiple streams across a high-speed serial link. |
jshamlet |
459d 08h |
/open8_urisc/trunk/VHDL/ |
308 |
|
jshamlet |
480d 22h |
/open8_urisc/trunk/VHDL/ |
307 |
Fixed comments on o8_version.vhd |
jshamlet |
688d 08h |
/open8_urisc/trunk/VHDL/ |
299 |
Modified the status_led.vhd to slow down the DIM50PCT signal to 1/32 instead of 1/2 for use with shift-register based discrete LEDs and added the ability to chain the toggle signal to save on resources as well as synchronize the "toggling" |
jshamlet |
696d 20h |
/open8_urisc/trunk/VHDL/ |
298 |
Fixed a long-standing bug in the SBC instruction where the 1 wasn't being added to complete the 2's complement of Rn. This was causing off-by-one errors in subtraction and negating carry only subtractions. |
jshamlet |
697d 22h |
/open8_urisc/trunk/VHDL/ |
297 |
Fixed register map comments |
jshamlet |
988d 06h |
/open8_urisc/trunk/VHDL/ |
296 |
Removed parallel interface from o8_vector_rx.vhd, modified vector_tx.vhd to use a generic for it's seed value, slight formatting change on o8_elapsed_usec.vhd. |
jshamlet |
996d 22h |
/open8_urisc/trunk/VHDL/ |
295 |
Undoing previous revision. UART was fine, bug reporter was not. |
jshamlet |
1000d 01h |
/open8_urisc/trunk/VHDL/ |
294 |
Fixed an ancient bug in the parity logic that had the parity inverted. |
jshamlet |
1000d 06h |
/open8_urisc/trunk/VHDL/ |
293 |
Fixed formatting issue in o8_sync_serial where tabs were inserted instead of spaces and fixed column spacing as a result (purely cosmetic) |
jshamlet |
1019d 06h |
/open8_urisc/trunk/VHDL/ |
292 |
Updated the o8_trig_delay entity by:
1) Added a global interrupt enable,
2) Added the ability to trigger on both the pre- and post-arm trigger input
3) Added the ability to read the external input on offset 7 |
jshamlet |
1090d 05h |
/open8_urisc/trunk/VHDL/ |
290 |
Added an additional generic "Rotation_Ignores_Carry" that removes the carry logic from the ROL/ROR instructions such that they now rotate 'normally',
Added an alias for PSR_GP4 named PSR_S, as it is now used to switch the function of the RSP instruction. The internal opcode hasn't changed, but it allows assembly code to use PSR_S or BRS/BNS when performing RSP related operations. |
jshamlet |
1132d 20h |
/open8_urisc/trunk/VHDL/ |
289 |
Added back the delay for the cursor home command, since it is slow on most Hitachi compatible LCD panels. |
jshamlet |
1150d 06h |
/open8_urisc/trunk/VHDL/ |
288 |
Removed hard-wired R/Wn output and replaced it with a note that the R/Wn line must be tied low either in firmware or on the board. |
jshamlet |
1151d 03h |
/open8_urisc/trunk/VHDL/ |
287 |
Fixed mangled comments and revisioning dates. |
jshamlet |
1152d 02h |
/open8_urisc/trunk/VHDL/ |
286 |
Added initial cut of a "universal" character LCD driver. Allows for adjustment of address setup, enable high, and cycle times. Also has built-in timers for handling timing on certain commands. |
jshamlet |
1152d 02h |
/open8_urisc/trunk/VHDL/ |
285 |
Added checksum byte to vector tx/rx to avoid issues with serial line noise glitching the receiver. Also modified the transmitted to take any generic argument, rather than canned arguments. |
jshamlet |
1159d 05h |
/open8_urisc/trunk/VHDL/ |
284 |
Corrected the vhdl unit name and description for o8_7seg.vhd |
jshamlet |
1272d 16h |
/open8_urisc/trunk/VHDL/ |
283 |
Altered SDLC bitclock check on TX to NOT block when tested by software, but to instead ignore packet write requests if BClk_Okay is low. This allows software to continue checking BClk_Okay in a polling loop. |
jshamlet |
1276d 04h |
/open8_urisc/trunk/VHDL/ |
282 |
Modified the SDLC core transmit states to have consistent naming. |
jshamlet |
1276d 04h |
/open8_urisc/trunk/VHDL/ |
281 |
Added pre-initialization to the dual-port RAM signals. |
jshamlet |
1276d 07h |
/open8_urisc/trunk/VHDL/ |
280 |
Got rid of silly aliases that connected the dual-port memory and the arbitration logic. |
jshamlet |
1276d 08h |
/open8_urisc/trunk/VHDL/ |
279 |
More comment cleanup |
jshamlet |
1277d 05h |
/open8_urisc/trunk/VHDL/ |