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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 325

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Rev Log message Author Age Path
325 Added the rest of the initializers to the signal assignments jshamlet 276d 17h /open8_urisc/trunk/VHDL/
324 Modified the Open8 version of the multi-channel roll average code to have separate interrupt enables for average and flush operations. Note that the flush status bit should be checked by software prior to use if the Autoflush_On_Reset generic is set TRUE.

Also adding the ROMTAPE entity, which acts as a serial-access ROM for storing strings, arrays, etc. in order to alleviate pressure on the primary program ROM. It is intended for use with loops that load fixed content from ROM.
jshamlet 276d 17h /open8_urisc/trunk/VHDL/
323 Forgot to add files jshamlet 277d 15h /open8_urisc/trunk/VHDL/
322 Performance fixes for the LCD interface,
Fixed incorrect entity name for the dual LTC2355 IF,
Added a CPU-accessible 8-channel averager core and FIFO-style ROM
jshamlet 277d 15h /open8_urisc/trunk/VHDL/
321 Fixed issue with parity flag in receiver sticking jshamlet 381d 08h /open8_urisc/trunk/VHDL/
320 Inverted flow control signals to match EIA-232 specification jshamlet 383d 11h /open8_urisc/trunk/VHDL/
319 Fixed off-by-one error in channel count jshamlet 384d 15h /open8_urisc/trunk/VHDL/
318 Added o8_scale_conv.vhd and intdiv.vhd jshamlet 388d 17h /open8_urisc/trunk/VHDL/
317 Altered the reinit signal on teh adc128s022.vhd driver to be optional, and removed the "dead" signal from the upper level o8_de0_nano_adc_if.vhd code. jshamlet 402d 13h /open8_urisc/trunk/VHDL/
316 More code cleanup and comments,
Removed INT_VECTOR_n constants, as they are superfluous. There are no reasonable situations in which the constants would be altered.
jshamlet 402d 13h /open8_urisc/trunk/VHDL/
315 Added Terasic DE0 Nano ADC interface and rolling averager. jshamlet 402d 14h /open8_urisc/trunk/VHDL/
314 Code cleanup and added comments jshamlet 402d 15h /open8_urisc/trunk/VHDL/
313 Added all generics to package component jshamlet 402d 17h /open8_urisc/trunk/VHDL/
312 Added o8_timer24.vhd as a more flexible alternative to o8_sys_timer_ii.vhd.
Also cleaned up some comments in the HTML documentation
jshamlet 402d 17h /open8_urisc/trunk/VHDL/
310 Added optional DACadv signal to advance the PWM engine using an external signal. This is used to synchronize the DAC with other DACs or for streaming multiple streams across a high-speed serial link. jshamlet 473d 19h /open8_urisc/trunk/VHDL/
308 jshamlet 495d 09h /open8_urisc/trunk/VHDL/
307 Fixed comments on o8_version.vhd jshamlet 702d 18h /open8_urisc/trunk/VHDL/
299 Modified the status_led.vhd to slow down the DIM50PCT signal to 1/32 instead of 1/2 for use with shift-register based discrete LEDs and added the ability to chain the toggle signal to save on resources as well as synchronize the "toggling" jshamlet 711d 06h /open8_urisc/trunk/VHDL/
298 Fixed a long-standing bug in the SBC instruction where the 1 wasn't being added to complete the 2's complement of Rn. This was causing off-by-one errors in subtraction and negating carry only subtractions. jshamlet 712d 08h /open8_urisc/trunk/VHDL/
297 Fixed register map comments jshamlet 1002d 17h /open8_urisc/trunk/VHDL/
296 Removed parallel interface from o8_vector_rx.vhd, modified vector_tx.vhd to use a generic for it's seed value, slight formatting change on o8_elapsed_usec.vhd. jshamlet 1011d 08h /open8_urisc/trunk/VHDL/
295 Undoing previous revision. UART was fine, bug reporter was not. jshamlet 1014d 12h /open8_urisc/trunk/VHDL/
294 Fixed an ancient bug in the parity logic that had the parity inverted. jshamlet 1014d 17h /open8_urisc/trunk/VHDL/
293 Fixed formatting issue in o8_sync_serial where tabs were inserted instead of spaces and fixed column spacing as a result (purely cosmetic) jshamlet 1033d 17h /open8_urisc/trunk/VHDL/
292 Updated the o8_trig_delay entity by:
1) Added a global interrupt enable,
2) Added the ability to trigger on both the pre- and post-arm trigger input
3) Added the ability to read the external input on offset 7
jshamlet 1104d 16h /open8_urisc/trunk/VHDL/
290 Added an additional generic "Rotation_Ignores_Carry" that removes the carry logic from the ROL/ROR instructions such that they now rotate 'normally',
Added an alias for PSR_GP4 named PSR_S, as it is now used to switch the function of the RSP instruction. The internal opcode hasn't changed, but it allows assembly code to use PSR_S or BRS/BNS when performing RSP related operations.
jshamlet 1147d 06h /open8_urisc/trunk/VHDL/
289 Added back the delay for the cursor home command, since it is slow on most Hitachi compatible LCD panels. jshamlet 1164d 17h /open8_urisc/trunk/VHDL/
288 Removed hard-wired R/Wn output and replaced it with a note that the R/Wn line must be tied low either in firmware or on the board. jshamlet 1165d 13h /open8_urisc/trunk/VHDL/
287 Fixed mangled comments and revisioning dates. jshamlet 1166d 12h /open8_urisc/trunk/VHDL/
286 Added initial cut of a "universal" character LCD driver. Allows for adjustment of address setup, enable high, and cycle times. Also has built-in timers for handling timing on certain commands. jshamlet 1166d 13h /open8_urisc/trunk/VHDL/

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