Rev |
Log message |
Author |
Age |
Path |
331 |
Added custom SPI LCD interface (pending receive side) and watchdog timer. Also modified system timer II to use aliases |
jshamlet |
257d 12h |
/open8_urisc/trunk/VHDL/ |
330 |
Updated to route RAM write fault signal and force CPU interrupts to task manager requirements. |
jshamlet |
263d 19h |
/open8_urisc/trunk/VHDL/ |
329 |
Added a core that specifically supports the task switcher software. It merges o8_int_mgr16 with a wide register, allowing full control of I/O peripherals by the task switcher software. This also allows the task switcher to be enabled for the full 16 I/O write qualification lines, which had previously only been supported in the task data setup. |
jshamlet |
263d 20h |
/open8_urisc/trunk/VHDL/ |
327 |
More bug fixes:
Added write qual line to LTC2355 interface, fixed bug where output data was duplicating the lower byte in the averager, added an initial romtape.hex file |
jshamlet |
264d 22h |
/open8_urisc/trunk/VHDL/ |
326 |
Minor comment correction |
jshamlet |
270d 19h |
/open8_urisc/trunk/VHDL/ |
325 |
Added the rest of the initializers to the signal assignments |
jshamlet |
270d 20h |
/open8_urisc/trunk/VHDL/ |
324 |
Modified the Open8 version of the multi-channel roll average code to have separate interrupt enables for average and flush operations. Note that the flush status bit should be checked by software prior to use if the Autoflush_On_Reset generic is set TRUE.
Also adding the ROMTAPE entity, which acts as a serial-access ROM for storing strings, arrays, etc. in order to alleviate pressure on the primary program ROM. It is intended for use with loops that load fixed content from ROM. |
jshamlet |
270d 20h |
/open8_urisc/trunk/VHDL/ |
323 |
Forgot to add files |
jshamlet |
271d 19h |
/open8_urisc/trunk/VHDL/ |
322 |
Performance fixes for the LCD interface,
Fixed incorrect entity name for the dual LTC2355 IF,
Added a CPU-accessible 8-channel averager core and FIFO-style ROM |
jshamlet |
271d 19h |
/open8_urisc/trunk/VHDL/ |
321 |
Fixed issue with parity flag in receiver sticking |
jshamlet |
375d 12h |
/open8_urisc/trunk/VHDL/ |
320 |
Inverted flow control signals to match EIA-232 specification |
jshamlet |
377d 15h |
/open8_urisc/trunk/VHDL/ |
319 |
Fixed off-by-one error in channel count |
jshamlet |
378d 18h |
/open8_urisc/trunk/VHDL/ |
318 |
Added o8_scale_conv.vhd and intdiv.vhd |
jshamlet |
382d 20h |
/open8_urisc/trunk/VHDL/ |
317 |
Altered the reinit signal on teh adc128s022.vhd driver to be optional, and removed the "dead" signal from the upper level o8_de0_nano_adc_if.vhd code. |
jshamlet |
396d 17h |
/open8_urisc/trunk/VHDL/ |
316 |
More code cleanup and comments,
Removed INT_VECTOR_n constants, as they are superfluous. There are no reasonable situations in which the constants would be altered. |
jshamlet |
396d 17h |
/open8_urisc/trunk/VHDL/ |
315 |
Added Terasic DE0 Nano ADC interface and rolling averager. |
jshamlet |
396d 18h |
/open8_urisc/trunk/VHDL/ |
314 |
Code cleanup and added comments |
jshamlet |
396d 19h |
/open8_urisc/trunk/VHDL/ |
313 |
Added all generics to package component |
jshamlet |
396d 20h |
/open8_urisc/trunk/VHDL/ |
312 |
Added o8_timer24.vhd as a more flexible alternative to o8_sys_timer_ii.vhd.
Also cleaned up some comments in the HTML documentation |
jshamlet |
396d 21h |
/open8_urisc/trunk/VHDL/ |
310 |
Added optional DACadv signal to advance the PWM engine using an external signal. This is used to synchronize the DAC with other DACs or for streaming multiple streams across a high-speed serial link. |
jshamlet |
467d 22h |
/open8_urisc/trunk/VHDL/ |
308 |
|
jshamlet |
489d 12h |
/open8_urisc/trunk/VHDL/ |
307 |
Fixed comments on o8_version.vhd |
jshamlet |
696d 22h |
/open8_urisc/trunk/VHDL/ |
299 |
Modified the status_led.vhd to slow down the DIM50PCT signal to 1/32 instead of 1/2 for use with shift-register based discrete LEDs and added the ability to chain the toggle signal to save on resources as well as synchronize the "toggling" |
jshamlet |
705d 10h |
/open8_urisc/trunk/VHDL/ |
298 |
Fixed a long-standing bug in the SBC instruction where the 1 wasn't being added to complete the 2's complement of Rn. This was causing off-by-one errors in subtraction and negating carry only subtractions. |
jshamlet |
706d 12h |
/open8_urisc/trunk/VHDL/ |
297 |
Fixed register map comments |
jshamlet |
996d 20h |
/open8_urisc/trunk/VHDL/ |
296 |
Removed parallel interface from o8_vector_rx.vhd, modified vector_tx.vhd to use a generic for it's seed value, slight formatting change on o8_elapsed_usec.vhd. |
jshamlet |
1005d 12h |
/open8_urisc/trunk/VHDL/ |
295 |
Undoing previous revision. UART was fine, bug reporter was not. |
jshamlet |
1008d 15h |
/open8_urisc/trunk/VHDL/ |
294 |
Fixed an ancient bug in the parity logic that had the parity inverted. |
jshamlet |
1008d 20h |
/open8_urisc/trunk/VHDL/ |
293 |
Fixed formatting issue in o8_sync_serial where tabs were inserted instead of spaces and fixed column spacing as a result (purely cosmetic) |
jshamlet |
1027d 20h |
/open8_urisc/trunk/VHDL/ |
292 |
Updated the o8_trig_delay entity by:
1) Added a global interrupt enable,
2) Added the ability to trigger on both the pre- and post-arm trigger input
3) Added the ability to read the external input on offset 7 |
jshamlet |
1098d 19h |
/open8_urisc/trunk/VHDL/ |