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[/] [openmsp430/] - Rev 107

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107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4848d 21h /openmsp430/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).
olivier.girard 4848d 22h /openmsp430/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.
olivier.girard 4863d 23h /openmsp430/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4868d 00h /openmsp430/
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.
olivier.girard 4869d 05h /openmsp430/
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+
olivier.girard 4869d 22h /openmsp430/
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 4870d 00h /openmsp430/
100 Update HTML documentation with Actel's FPGA implementation example (file & directory description section). olivier.girard 4872d 23h /openmsp430/
99 Small fix for CVER simulator support. olivier.girard 4874d 00h /openmsp430/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.
olivier.girard 4874d 00h /openmsp430/
97 Update Tools' Windows executables with EraseROM command fix. olivier.girard 4874d 23h /openmsp430/
96 Fixed EraseROM command in the TCL library of the Software development tools. olivier.girard 4875d 00h /openmsp430/
95 Update some test patterns for the additional simulator supports. olivier.girard 4877d 23h /openmsp430/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim
olivier.girard 4877d 23h /openmsp430/
93 Update Tools' Windows executables. olivier.girard 4881d 23h /openmsp430/
92 Fixed bug where the openmsp430-minidebug application shows data memory size instead of program memory size and program memory size instead of data memory size.
Thanks to "dir" for reporting the bug :-)
olivier.girard 4882d 00h /openmsp430/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.
olivier.girard 4882d 00h /openmsp430/
90 Update windows executables for the tools. olivier.girard 4897d 06h /openmsp430/
89 Update the loader tool to support Intel-HEX format. olivier.girard 4897d 06h /openmsp430/
88 Update windows executables for the tools. olivier.girard 4897d 06h /openmsp430/
87 Minor update of gdbproxy to allow sourcing some custom tcl scripts.
Major update of the minidebugger (complete re-work of the GUI).
olivier.girard 4897d 06h /openmsp430/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4904d 21h /openmsp430/
85 Diverse RTL cosmetic updates. olivier.girard 4904d 23h /openmsp430/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.
olivier.girard 4910d 00h /openmsp430/
83 Add Oscilloscope screenshot + link to the original game. olivier.girard 4956d 00h /openmsp430/
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories
olivier.girard 4956d 00h /openmsp430/
81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 4958d 22h /openmsp430/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4959d 07h /openmsp430/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4971d 00h /openmsp430/
78 update windows executable files olivier.girard 4973d 00h /openmsp430/

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