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[/] [openmsp430/] - Rev 125

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125 update changelog... olivier.girard 4637d 20h /openmsp430/
124 Improved gdbproxy robustness.
Create a workaround to prevent GDB from freezing when single-stepping on a LPMx or a "JMP $-0" instruction.		 olivier.girard 4638d 07h /openmsp430/
123 update changelog... olivier.girard 4659d 19h /openmsp430/
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4659d 19h /openmsp430/
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)		 olivier.girard 4731d 19h /openmsp430/
120 update tools changelog... olivier.girard 4763d 02h /openmsp430/
119 Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin. olivier.girard 4763d 02h /openmsp430/
118 Changelog update (move to modified BSD license). olivier.girard 4763d 19h /openmsp430/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4763d 20h /openmsp430/
116 Update documentation to reflect the latest core updates. olivier.girard 4779d 20h /openmsp430/
115 Add linker script example. olivier.girard 4788d 19h /openmsp430/
114 Improved the VerifyCPU_ID procedure. olivier.girard 4791d 19h /openmsp430/
113 Created ChangeLog files... olivier.girard 4792d 19h /openmsp430/
112 Modified comment. olivier.girard 4796d 18h /openmsp430/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4797d 18h /openmsp430/
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.		 olivier.girard 4798d 18h /openmsp430/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4852d 03h /openmsp430/
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4853d 16h /openmsp430/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4853d 16h /openmsp430/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4853d 17h /openmsp430/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4868d 18h /openmsp430/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4872d 19h /openmsp430/
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4874d 00h /openmsp430/
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+		 olivier.girard 4874d 17h /openmsp430/
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 4874d 19h /openmsp430/
100 Update HTML documentation with Actel's FPGA implementation example (file & directory description section). olivier.girard 4877d 18h /openmsp430/
99 Small fix for CVER simulator support. olivier.girard 4878d 19h /openmsp430/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4878d 19h /openmsp430/
97 Update Tools' Windows executables with EraseROM command fix. olivier.girard 4879d 18h /openmsp430/
96 Fixed EraseROM command in the TCL library of the Software development tools. olivier.girard 4879d 19h /openmsp430/

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