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[/] [openmsp430/] - Rev 133

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133 Add support for new CPU version. olivier.girard 4463d 09h /openmsp430/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4476d 09h /openmsp430/
131 Update ChangeLog olivier.girard 4484d 08h /openmsp430/
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 4484d 08h /openmsp430/
129 Update ChangeLog olivier.girard 4560d 09h /openmsp430/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4560d 09h /openmsp430/
127 update changelog... olivier.girard 4596d 08h /openmsp430/
126 Remove freewrap642 directory.
Tools users now have to install TCL/TK instead.		 olivier.girard 4596d 08h /openmsp430/
125 update changelog... olivier.girard 4610d 11h /openmsp430/
124 Improved gdbproxy robustness.
Create a workaround to prevent GDB from freezing when single-stepping on a LPMx or a "JMP $-0" instruction.		 olivier.girard 4610d 22h /openmsp430/
123 update changelog... olivier.girard 4632d 09h /openmsp430/
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4632d 09h /openmsp430/
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)		 olivier.girard 4704d 10h /openmsp430/
120 update tools changelog... olivier.girard 4735d 17h /openmsp430/
119 Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin. olivier.girard 4735d 17h /openmsp430/
118 Changelog update (move to modified BSD license). olivier.girard 4736d 10h /openmsp430/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4736d 10h /openmsp430/
116 Update documentation to reflect the latest core updates. olivier.girard 4752d 11h /openmsp430/
115 Add linker script example. olivier.girard 4761d 10h /openmsp430/
114 Improved the VerifyCPU_ID procedure. olivier.girard 4764d 10h /openmsp430/
113 Created ChangeLog files... olivier.girard 4765d 10h /openmsp430/
112 Modified comment. olivier.girard 4769d 09h /openmsp430/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4770d 09h /openmsp430/
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.		 olivier.girard 4771d 09h /openmsp430/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4824d 18h /openmsp430/
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4826d 07h /openmsp430/
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4826d 07h /openmsp430/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4826d 08h /openmsp430/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4841d 09h /openmsp430/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4845d 10h /openmsp430/

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