| Rev |
Log message |
Author |
Age |
Path |
| 106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4824d 01h |
/openmsp430/trunk/core/sim/ |
| 105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4839d 02h |
/openmsp430/trunk/core/sim/ |
| 103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4844d 08h |
/openmsp430/trunk/core/sim/ |
| 102 |
Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:
- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+ |
olivier.girard |
4845d 01h |
/openmsp430/trunk/core/sim/ |
| 101 |
Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. |
olivier.girard |
4845d 02h |
/openmsp430/trunk/core/sim/ |
| 99 |
Small fix for CVER simulator support. |
olivier.girard |
4849d 02h |
/openmsp430/trunk/core/sim/ |
| 98 |
Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated. |
olivier.girard |
4849d 02h |
/openmsp430/trunk/core/sim/ |
| 95 |
Update some test patterns for the additional simulator supports. |
olivier.girard |
4853d 02h |
/openmsp430/trunk/core/sim/ |
| 94 |
Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim |
olivier.girard |
4853d 02h |
/openmsp430/trunk/core/sim/ |
| 91 |
Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface. |
olivier.girard |
4857d 03h |
/openmsp430/trunk/core/sim/ |
| 86 |
Update serial debug interface test patterns to make them work with all program memory configurations. |
olivier.girard |
4880d 00h |
/openmsp430/trunk/core/sim/ |
| 85 |
Diverse RTL cosmetic updates. |
olivier.girard |
4880d 02h |
/openmsp430/trunk/core/sim/ |
| 80 |
Create initial version of the Actel FPGA implementation example. |
olivier.girard |
4934d 09h |
/openmsp430/trunk/core/sim/ |
| 79 |
Update the GPIO peripheral to fix a potential synchronization issue. |
olivier.girard |
4946d 03h |
/openmsp430/trunk/core/sim/ |
| 76 |
Add possibility to simulate C code within the "core" environment. |
olivier.girard |
4951d 02h |
/openmsp430/trunk/core/sim/ |
| 74 |
Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly. |
olivier.girard |
5033d 03h |
/openmsp430/trunk/core/sim/ |
| 73 |
Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell. |
olivier.girard |
5058d 03h |
/openmsp430/trunk/core/sim/ |
| 72 |
Expand configurability options of the program and data memory sizes. |
olivier.girard |
5060d 04h |
/openmsp430/trunk/core/sim/ |
| 67 |
Added 16x16 Hardware Multiplier. |
olivier.girard |
5207d 11h |
/openmsp430/trunk/core/sim/ |
| 65 |
Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. |
olivier.girard |
5218d 01h |
/openmsp430/trunk/core/sim/ |
| 58 |
Update the debug hardware breakpoint verification patterns to reflect the latest design updates. |
olivier.girard |
5241d 00h |
/openmsp430/trunk/core/sim/ |
| 55 |
Add a "sandbox" test pattern to play around with the simulation :-P |
olivier.girard |
5246d 02h |
/openmsp430/trunk/core/sim/ |
| 54 |
Update FPGA projects with the combinatorial loop fixed. |
olivier.girard |
5246d 04h |
/openmsp430/trunk/core/sim/ |
| 37 |
|
olivier.girard |
5275d 02h |
/openmsp430/trunk/core/sim/ |
| 34 |
To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. |
olivier.girard |
5275d 04h |
/openmsp430/trunk/core/sim/ |
| 33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5275d 04h |
/openmsp430/trunk/core/sim/ |
| 23 |
Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct). |
olivier.girard |
5396d 06h |
/openmsp430/trunk/core/sim/ |
| 19 |
added SVN property for keywords |
olivier.girard |
5422d 01h |
/openmsp430/trunk/core/sim/ |
| 18 |
Updated headers with SVN info |
olivier.girard |
5422d 01h |
/openmsp430/trunk/core/sim/ |
| 17 |
Updated header with SVN info |
olivier.girard |
5422d 01h |
/openmsp430/trunk/core/sim/ |
