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[/] [openmsp430/] [trunk/] [fpga/] - Rev 78

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74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5084d 21h /openmsp430/trunk/fpga/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5109d 22h /openmsp430/trunk/fpga/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5111d 22h /openmsp430/trunk/fpga/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5258d 21h /openmsp430/trunk/fpga/
61 Update openMSP430 rtl. olivier.girard 5290d 19h /openmsp430/trunk/fpga/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5292d 18h /openmsp430/trunk/fpga/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5297d 23h /openmsp430/trunk/fpga/
43 Re-add documentation (earlier pdf was broken). olivier.girard 5326d 19h /openmsp430/trunk/fpga/
42 olivier.girard 5326d 19h /openmsp430/trunk/fpga/
41 Update bitstream & SVN ignore patterns. olivier.girard 5326d 19h /openmsp430/trunk/fpga/
40 Minor updates. olivier.girard 5326d 19h /openmsp430/trunk/fpga/
39 Update FPGA projects with new openMSP430 core. olivier.girard 5326d 19h /openmsp430/trunk/fpga/
38 Remove old core version. olivier.girard 5326d 20h /openmsp430/trunk/fpga/
37 olivier.girard 5326d 20h /openmsp430/trunk/fpga/
36 Remove old core version. olivier.girard 5326d 21h /openmsp430/trunk/fpga/
32 Minor update to the HTML documentation + add some SVN ignore properties to the Altera FPGA project simulation directory. olivier.girard 5328d 19h /openmsp430/trunk/fpga/
30 Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution). olivier.girard 5328d 20h /openmsp430/trunk/fpga/
29 Add Altera Cyclone II FPGA project example. olivier.girard 5328d 21h /openmsp430/trunk/fpga/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5337d 04h /openmsp430/trunk/fpga/
27 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5337d 04h /openmsp430/trunk/fpga/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5337d 05h /openmsp430/trunk/fpga/
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5427d 02h /openmsp430/trunk/fpga/
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5427d 02h /openmsp430/trunk/fpga/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5448d 00h /openmsp430/trunk/fpga/
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5473d 19h /openmsp430/trunk/fpga/
16 Updated header with SVN info olivier.girard 5473d 20h /openmsp430/trunk/fpga/
5 Added some ignore pattern properties... olivier.girard 5495d 21h /openmsp430/trunk/fpga/
3 update FPGA inc file to match the CORE version olivier.girard 5508d 08h /openmsp430/trunk/fpga/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5508d 20h /openmsp430/trunk/fpga/

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