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[/] [openmsp430/] [trunk/] [fpga/] - Rev 80

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Rev Log message Author Age Path
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4936d 13h /openmsp430/trunk/fpga/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4948d 07h /openmsp430/trunk/fpga/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5035d 06h /openmsp430/trunk/fpga/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5060d 07h /openmsp430/trunk/fpga/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5062d 07h /openmsp430/trunk/fpga/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5209d 06h /openmsp430/trunk/fpga/
61 Update openMSP430 rtl. olivier.girard 5241d 04h /openmsp430/trunk/fpga/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5243d 03h /openmsp430/trunk/fpga/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5248d 08h /openmsp430/trunk/fpga/
43 Re-add documentation (earlier pdf was broken). olivier.girard 5277d 04h /openmsp430/trunk/fpga/
42 olivier.girard 5277d 04h /openmsp430/trunk/fpga/
41 Update bitstream & SVN ignore patterns. olivier.girard 5277d 04h /openmsp430/trunk/fpga/
40 Minor updates. olivier.girard 5277d 05h /openmsp430/trunk/fpga/
39 Update FPGA projects with new openMSP430 core. olivier.girard 5277d 05h /openmsp430/trunk/fpga/
38 Remove old core version. olivier.girard 5277d 05h /openmsp430/trunk/fpga/
37 olivier.girard 5277d 05h /openmsp430/trunk/fpga/
36 Remove old core version. olivier.girard 5277d 06h /openmsp430/trunk/fpga/
32 Minor update to the HTML documentation + add some SVN ignore properties to the Altera FPGA project simulation directory. olivier.girard 5279d 04h /openmsp430/trunk/fpga/
30 Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution). olivier.girard 5279d 05h /openmsp430/trunk/fpga/
29 Add Altera Cyclone II FPGA project example. olivier.girard 5279d 06h /openmsp430/trunk/fpga/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5287d 14h /openmsp430/trunk/fpga/
27 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5287d 14h /openmsp430/trunk/fpga/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5287d 14h /openmsp430/trunk/fpga/
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5377d 11h /openmsp430/trunk/fpga/
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5377d 12h /openmsp430/trunk/fpga/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5398d 10h /openmsp430/trunk/fpga/
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5424d 04h /openmsp430/trunk/fpga/
16 Updated header with SVN info olivier.girard 5424d 05h /openmsp430/trunk/fpga/
5 Added some ignore pattern properties... olivier.girard 5446d 06h /openmsp430/trunk/fpga/
3 update FPGA inc file to match the CORE version olivier.girard 5458d 17h /openmsp430/trunk/fpga/

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