OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] - Rev 157

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4273d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
153 Update XFLOW scripts to bring more automation.
Several bitstreams are now checked in for direct use.		 olivier.girard 4328d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4358d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4361d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4432d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4448d 21h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
136 Update all FPGA projects with the latest core version. olivier.girard 4480d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4493d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4577d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
112 Modified comment. olivier.girard 4786d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4787d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4841d 20h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4843d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4858d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4862d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4868d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4872d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4876d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4899d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
85 Diverse RTL cosmetic updates. olivier.girard 4899d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4904d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4965d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5052d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5077d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5079d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5226d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
61 Update openMSP430 rtl. olivier.girard 5258d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5260d 09h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5265d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/
40 Minor updates. olivier.girard 5294d 10h /openmsp430/trunk/fpga/xilinx_diligent_s3board/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.