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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] - Rev 167

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155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4295d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4380d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4383d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
136 Update all FPGA projects with the latest core version. olivier.girard 4502d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4515d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4599d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
112 Modified comment. olivier.girard 4808d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4809d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4863d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4880d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4884d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4898d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4921d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
85 Diverse RTL cosmetic updates. olivier.girard 4921d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4926d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4987d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5074d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5101d 04h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5248d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
61 Update openMSP430 rtl. olivier.girard 5280d 01h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5282d 00h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5287d 05h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
37 olivier.girard 5316d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
36 Remove old core version. olivier.girard 5316d 03h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5326d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5326d 11h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5437d 07h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
16 Updated header with SVN info olivier.girard 5463d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
3 update FPGA inc file to match the CORE version olivier.girard 5497d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5498d 02h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/

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