OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 119

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
119 Updated to clarify exceptions for division and details of multiplication. jeremybennett 5135d 14h /openrisc/
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5136d 00h /openrisc/
117 Updates on l.ff1, l.fl1 and l.maci. jeremybennett 5138d 02h /openrisc/
116 Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time. jeremybennett 5138d 03h /openrisc/
115 Added support for l.fl1 and tests for l.ff1 and l.fl1 jeremybennett 5139d 03h /openrisc/
114 l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR. jeremybennett 5139d 04h /openrisc/
113 Updates to exception handling for l.add and l.div jeremybennett 5140d 02h /openrisc/
112 Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register. jeremybennett 5140d 02h /openrisc/
111 Changed conditionals for Verilator to "verilator" instead of "VERILATOR". jeremybennett 5140d 07h /openrisc/
110 or1ksim make check should work without a libc in the or32-elf tools julius 5141d 04h /openrisc/
109 or_debug_proxy does signals with signals, just ignores signals julius 5141d 12h /openrisc/
108 Updated to clarify overflow and exceptions for l.add, l.addc, l.addi, l.addic, l.div and l.divu. jeremybennett 5143d 02h /openrisc/
107 New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug. jeremybennett 5143d 03h /openrisc/
106 Removing old tests, pending addition of new ones. jeremybennett 5143d 03h /openrisc/
105 Tagging the 0.4.0rc1 candidate release of Or1ksim jeremybennett 5146d 10h /openrisc/
104 Candidate release 0.4.0rc4 jeremybennett 5146d 10h /openrisc/
103 Updated to clarify lf.madd.d and lf.madd.s opcodes. jeremybennett 5147d 07h /openrisc/
102 added linux-2.6.34 and uClibc-0.9.31 patch file marcus.erlandsson 5153d 14h /openrisc/
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5155d 04h /openrisc/
100 Single precision FPU stuff for or1ksim julius 5155d 06h /openrisc/
99 Bug in test evaluation for library fixed. jeremybennett 5160d 04h /openrisc/
98 Comprehensive testing of the library JTAG interface. Updates to the documentation to warn of issues in using the memory controller. jeremybennett 5161d 06h /openrisc/
97 Updates to test the new JTAG library interface (not yet complete). jeremybennett 5175d 12h /openrisc/
96 Various changes which had not been picked up in earlier commits. jeremybennett 5176d 13h /openrisc/
95 Some tidy ups to the DejaGNU testing.

All Mark Jarvin's fixes for Mac OS X.
jeremybennett 5178d 05h /openrisc/
94 Finally added byte reading to or_debug_proxy julius 5181d 01h /openrisc/
93 Additional library tests. Key difference is change to Or1ksim library interface for upcalls to bring closer in to line with SystemC TLM 2.0. jeremybennett 5182d 03h /openrisc/
92 Initial version of documents to capture additional information, particularly about the OpenRISC 1200 version 2. jeremybennett 5183d 04h /openrisc/
91 Tidy up of some obsolete configuration code. jeremybennett 5189d 02h /openrisc/
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5189d 03h /openrisc/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.