OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 396

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
396 ORPSoCv2 final software fixes...for now. See updated README julius 5003d 15h /openrisc/
395 ORPSoCv2 moving ethernet tests to correct place julius 5003d 15h /openrisc/
394 ORPSoCv2 removing unused directories julius 5003d 15h /openrisc/
393 ORPSoCv2 software rearrangement in progress. Basic tests should now run again. julius 5003d 15h /openrisc/
392 ORPSoCv2 software path reorganisation stage 1. julius 5004d 07h /openrisc/
391 Removing modules no longer needed in ORPSoCv2 julius 5005d 08h /openrisc/
390 Updated toolchain build scripts to use FTP server on OpenCores.org. julius 5005d 08h /openrisc/
389 SD-Card boot added (sdboot) to the commands in the load file. DOS-filesystem added to support Fat12-16. Driver for SD-card added, SD and SDHC supported
Currently hardcoded to boot from vmlinux.bin		 tac2 5015d 16h /openrisc/
388 Tagging the 0.5.0rc2 candidate release of Or1ksim jeremybennett 5028d 15h /openrisc/
387 Fixed testing, to always use our DEJAGNU config. jeremybennett 5028d 15h /openrisc/
386 Updated for release 0.5.0rc2 jeremybennett 5028d 15h /openrisc/
385 Updates for Or1ksim 0.5.0rc2.

* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.

* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected.		 jeremybennett 5028d 15h /openrisc/
384 Tagging the 1.0rc2 candidate release of GCC 4.5.1 jeremybennett 5029d 16h /openrisc/
383 Adding makeinfo as a required tool to crossbuild-1.0.sh script julius 5029d 19h /openrisc/
382 New uClibc patch - to be built with 1.0 toolchain julius 5030d 13h /openrisc/
381 Crossbuild script for 1.0 updated to use new GCC rc2 patch and linux-2.6.35 julius 5030d 13h /openrisc/
380 Adding new Linux-2.6.35 patch, to be built with new 1.0 toolchain julius 5030d 13h /openrisc/
379 Linux-2.6.34 patch update - ethernet stability fix and USB host (ohs900) startup device detect improvement julius 5030d 14h /openrisc/
378 Adding gcc-4.5.1 patches to enable kernel to build again julius 5030d 18h /openrisc/
377 gcc-4.5.1/gcc/config/or32/or32.c:
Swap INTVAL for REGNO in or32_legitimate_address_p fixing 64-bit
machine build errors.		 julius 5031d 10h /openrisc/
376 Adding handling cases for RSP queries seen from new gdb-7.2 in RSP servers in
or1ksim and or_debug_proxy.

Adding ChangeLog to or_debug_proxy		 julius 5035d 21h /openrisc/
375 ORPmon update for compatibility with OR toolchain 1.0rc1 julius 5036d 14h /openrisc/
374 ORPSoCv2 adding some files forgotten from last checkin julius 5036d 14h /openrisc/
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 5036d 14h /openrisc/
372 Toolchain install script uClibc variable update julius 5036d 17h /openrisc/
371 Toolchain install script binutils commented out fix julius 5036d 18h /openrisc/
370 Toolchain install script uclibc url fix julius 5036d 18h /openrisc/
369 Toolchain build script binutils path fix julius 5036d 18h /openrisc/
368 Toolchain script: adding sim url path julius 5036d 19h /openrisc/
367 Fixup 1.0 release script julius 5036d 19h /openrisc/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.