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Rev Log message Author Age Path
463 ORPmon update julius 4904d 15h /openrisc/
462 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.

RAM models updated.		 julius 4904d 20h /openrisc/
461 Updated to be much stricter about usage. jeremybennett 4906d 15h /openrisc/
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4906d 16h /openrisc/
459 Add option to bld-all.sh to explicitly set control load of make, and fix typos. julius 4906d 23h /openrisc/
458 or1ksim testsuite updates julius 4907d 21h /openrisc/
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4916d 11h /openrisc/
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4916d 12h /openrisc/
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 4920d 14h /openrisc/
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 4922d 16h /openrisc/
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 4923d 03h /openrisc/
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 4923d 11h /openrisc/
451 More tidying up. jeremybennett 4927d 07h /openrisc/
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4927d 11h /openrisc/
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 4929d 08h /openrisc/
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 4929d 18h /openrisc/
447 Updates to register order. jeremybennett 4930d 11h /openrisc/
446 gdb-7.2 gdbserver updates. julius 4931d 06h /openrisc/
445 gdbserver update to use kernel port ptrace register definitions. julius 4932d 03h /openrisc/
444 Changes to ABI handling of varargs. jeremybennett 4932d 11h /openrisc/
443 Work in progress on more efficient Ethernet. jeremybennett 4932d 15h /openrisc/
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4933d 05h /openrisc/
441 Changes for gdbserver. jeremybennett 4933d 12h /openrisc/
440 Updated documentation to describe new Ethernet usage. jeremybennett 4934d 07h /openrisc/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4936d 11h /openrisc/
438 Fix to newlib header and library locations. jeremybennett 4939d 12h /openrisc/
437 Or1ksim - ethernet peripheral update, working much better. julius 4942d 01h /openrisc/
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 4943d 02h /openrisc/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4943d 02h /openrisc/
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 4946d 08h /openrisc/

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