Rev |
Log message |
Author |
Age |
Path |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4918d 03h |
/openrisc/ |
476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4918d 20h |
/openrisc/ |
475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4918d 23h |
/openrisc/ |
474 |
uC/OS-II port linker flags updated. |
julius |
4919d 05h |
/openrisc/ |
473 |
Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux. |
jeremybennett |
4919d 23h |
/openrisc/ |
472 |
Various changes which improve the quality of the tracing. |
jeremybennett |
4920d 01h |
/openrisc/ |
471 |
Adding ucos-ii port. |
julius |
4922d 04h |
/openrisc/ |
470 |
ORPSoC OR1200 crt0 updates. |
julius |
4922d 23h |
/openrisc/ |
469 |
newlib update - added zeroing of r0 to crt0.S |
julius |
4924d 00h |
/openrisc/ |
468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
4924d 00h |
/openrisc/ |
467 |
ORPmon - bug fixes and clean up. |
julius |
4924d 22h |
/openrisc/ |
466 |
ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README |
julius |
4925d 03h |
/openrisc/ |
465 |
ORPSoC SPI flash load Makefile and README updates. |
julius |
4925d 17h |
/openrisc/ |
464 |
More ORPmon updates. |
julius |
4925d 18h |
/openrisc/ |
463 |
ORPmon update |
julius |
4925d 21h |
/openrisc/ |
462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4926d 02h |
/openrisc/ |
461 |
Updated to be much stricter about usage. |
jeremybennett |
4927d 22h |
/openrisc/ |
460 |
Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. |
jeremybennett |
4927d 23h |
/openrisc/ |
459 |
Add option to bld-all.sh to explicitly set control load of make, and fix typos. |
julius |
4928d 05h |
/openrisc/ |
458 |
or1ksim testsuite updates |
julius |
4929d 03h |
/openrisc/ |
457 |
or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. |
julius |
4937d 17h |
/openrisc/ |
456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
4937d 19h |
/openrisc/ |
455 |
Updated to support threads. Does require thread debugging enabled in uClibc. |
jeremybennett |
4941d 21h |
/openrisc/ |
454 |
Updated to incorporate pthreads for Linux tool chain. |
jeremybennett |
4943d 23h |
/openrisc/ |
453 |
Updates to support constructor/destructor initialization for uClibc. |
jeremybennett |
4944d 09h |
/openrisc/ |
452 |
Update to define __UCLIBC__ when using the uClibc tool chain. |
jeremybennett |
4944d 18h |
/openrisc/ |
451 |
More tidying up. |
jeremybennett |
4948d 14h |
/openrisc/ |
450 |
Simplified (and hopefully more reliable) Ethernet MAC/PHY. |
jeremybennett |
4948d 17h |
/openrisc/ |
449 |
ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.
Replace use of "clean-all" with "distclean" as make rule to clean things. |
julius |
4950d 14h |
/openrisc/ |
448 |
Changed or32 to openrisc as Linux architecture name. |
jeremybennett |
4951d 00h |
/openrisc/ |