Rev |
Log message |
Author |
Age |
Path |
479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4905d 13h |
/openrisc/ |
478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4907d 05h |
/openrisc/ |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4907d 13h |
/openrisc/ |
476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4908d 06h |
/openrisc/ |
475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4908d 09h |
/openrisc/ |
474 |
uC/OS-II port linker flags updated. |
julius |
4908d 15h |
/openrisc/ |
473 |
Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux. |
jeremybennett |
4909d 09h |
/openrisc/ |
472 |
Various changes which improve the quality of the tracing. |
jeremybennett |
4909d 10h |
/openrisc/ |
471 |
Adding ucos-ii port. |
julius |
4911d 13h |
/openrisc/ |
470 |
ORPSoC OR1200 crt0 updates. |
julius |
4912d 09h |
/openrisc/ |
469 |
newlib update - added zeroing of r0 to crt0.S |
julius |
4913d 10h |
/openrisc/ |
468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
4913d 10h |
/openrisc/ |
467 |
ORPmon - bug fixes and clean up. |
julius |
4914d 07h |
/openrisc/ |
466 |
ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README |
julius |
4914d 13h |
/openrisc/ |
465 |
ORPSoC SPI flash load Makefile and README updates. |
julius |
4915d 03h |
/openrisc/ |
464 |
More ORPmon updates. |
julius |
4915d 04h |
/openrisc/ |
463 |
ORPmon update |
julius |
4915d 07h |
/openrisc/ |
462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4915d 12h |
/openrisc/ |
461 |
Updated to be much stricter about usage. |
jeremybennett |
4917d 07h |
/openrisc/ |
460 |
Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. |
jeremybennett |
4917d 09h |
/openrisc/ |
459 |
Add option to bld-all.sh to explicitly set control load of make, and fix typos. |
julius |
4917d 15h |
/openrisc/ |
458 |
or1ksim testsuite updates |
julius |
4918d 13h |
/openrisc/ |
457 |
or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. |
julius |
4927d 03h |
/openrisc/ |
456 |
ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. |
julius |
4927d 05h |
/openrisc/ |
455 |
Updated to support threads. Does require thread debugging enabled in uClibc. |
jeremybennett |
4931d 07h |
/openrisc/ |
454 |
Updated to incorporate pthreads for Linux tool chain. |
jeremybennett |
4933d 08h |
/openrisc/ |
453 |
Updates to support constructor/destructor initialization for uClibc. |
jeremybennett |
4933d 19h |
/openrisc/ |
452 |
Update to define __UCLIBC__ when using the uClibc tool chain. |
jeremybennett |
4934d 03h |
/openrisc/ |
451 |
More tidying up. |
jeremybennett |
4937d 23h |
/openrisc/ |
450 |
Simplified (and hopefully more reliable) Ethernet MAC/PHY. |
jeremybennett |
4938d 03h |
/openrisc/ |