Rev |
Log message |
Author |
Age |
Path |
491 |
ORPSoC or1200_monitor update. |
julius |
4871d 21h |
/openrisc/ |
490 |
Updates to fix spurious test failures and register scheduling. |
jeremybennett |
4876d 03h |
/openrisc/ |
489 |
ORPSoC sw cleanup. Remove warnings. |
julius |
4881d 10h |
/openrisc/ |
488 |
ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. |
julius |
4881d 10h |
/openrisc/ |
487 |
ORPSoC main software makefile update |
julius |
4884d 08h |
/openrisc/ |
486 |
ORPSoC updates, mainly software, i2c driver |
julius |
4884d 08h |
/openrisc/ |
485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4888d 13h |
/openrisc/ |
484 |
Changes to make r12 call-saved and to bring wchar tests in line. |
jeremybennett |
4889d 11h |
/openrisc/ |
483 |
Updated with new opcodes to generate random numbers and to identify us as Or1ksim. |
jeremybennett |
4891d 13h |
/openrisc/ |
482 |
Don't hardcode tool versions in help text |
olof |
4893d 01h |
/openrisc/ |
481 |
OR1200 Update. RTL and spec. |
julius |
4904d 19h |
/openrisc/ |
480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
4905d 17h |
/openrisc/ |
479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4906d 17h |
/openrisc/ |
478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4908d 08h |
/openrisc/ |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4908d 16h |
/openrisc/ |
476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4909d 10h |
/openrisc/ |
475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4909d 12h |
/openrisc/ |
474 |
uC/OS-II port linker flags updated. |
julius |
4909d 18h |
/openrisc/ |
473 |
Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux. |
jeremybennett |
4910d 13h |
/openrisc/ |
472 |
Various changes which improve the quality of the tracing. |
jeremybennett |
4910d 14h |
/openrisc/ |
471 |
Adding ucos-ii port. |
julius |
4912d 17h |
/openrisc/ |
470 |
ORPSoC OR1200 crt0 updates. |
julius |
4913d 12h |
/openrisc/ |
469 |
newlib update - added zeroing of r0 to crt0.S |
julius |
4914d 13h |
/openrisc/ |
468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
4914d 13h |
/openrisc/ |
467 |
ORPmon - bug fixes and clean up. |
julius |
4915d 11h |
/openrisc/ |
466 |
ORPSoC updates:
Add new test to determine processor's capabilities.
Fix up typo in example in spiflash app README |
julius |
4915d 17h |
/openrisc/ |
465 |
ORPSoC SPI flash load Makefile and README updates. |
julius |
4916d 07h |
/openrisc/ |
464 |
More ORPmon updates. |
julius |
4916d 08h |
/openrisc/ |
463 |
ORPmon update |
julius |
4916d 10h |
/openrisc/ |
462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4916d 15h |
/openrisc/ |