Rev |
Log message |
Author |
Age |
Path |
497 |
or_debug_proxy updates |
julius |
4891d 08h |
/openrisc/ |
496 |
ORPSoC ml501 updates - increased frequency, updated documentation |
julius |
4891d 09h |
/openrisc/ |
495 |
ORPSoC adding more accessor functions to Micron SDRAM model. |
julius |
4891d 09h |
/openrisc/ |
494 |
Change to ensure handles ctrl-C correctly with empty line. |
jeremybennett |
4902d 03h |
/openrisc/ |
493 |
ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. |
julius |
4904d 11h |
/openrisc/ |
492 |
ORPSoC VPI interface for modelsim and documentation update |
julius |
4905d 09h |
/openrisc/ |
491 |
ORPSoC or1200_monitor update. |
julius |
4905d 20h |
/openrisc/ |
490 |
Updates to fix spurious test failures and register scheduling. |
jeremybennett |
4910d 02h |
/openrisc/ |
489 |
ORPSoC sw cleanup. Remove warnings. |
julius |
4915d 09h |
/openrisc/ |
488 |
ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. |
julius |
4915d 09h |
/openrisc/ |
487 |
ORPSoC main software makefile update |
julius |
4918d 07h |
/openrisc/ |
486 |
ORPSoC updates, mainly software, i2c driver |
julius |
4918d 07h |
/openrisc/ |
485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4922d 12h |
/openrisc/ |
484 |
Changes to make r12 call-saved and to bring wchar tests in line. |
jeremybennett |
4923d 10h |
/openrisc/ |
483 |
Updated with new opcodes to generate random numbers and to identify us as Or1ksim. |
jeremybennett |
4925d 12h |
/openrisc/ |
482 |
Don't hardcode tool versions in help text |
olof |
4927d 00h |
/openrisc/ |
481 |
OR1200 Update. RTL and spec. |
julius |
4938d 18h |
/openrisc/ |
480 |
ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. |
julius |
4939d 16h |
/openrisc/ |
479 |
ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. |
julius |
4940d 15h |
/openrisc/ |
478 |
ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups. |
julius |
4942d 07h |
/openrisc/ |
477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4942d 15h |
/openrisc/ |
476 |
ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more. |
julius |
4943d 08h |
/openrisc/ |
475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4943d 11h |
/openrisc/ |
474 |
uC/OS-II port linker flags updated. |
julius |
4943d 17h |
/openrisc/ |
473 |
Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux. |
jeremybennett |
4944d 11h |
/openrisc/ |
472 |
Various changes which improve the quality of the tracing. |
jeremybennett |
4944d 13h |
/openrisc/ |
471 |
Adding ucos-ii port. |
julius |
4946d 16h |
/openrisc/ |
470 |
ORPSoC OR1200 crt0 updates. |
julius |
4947d 11h |
/openrisc/ |
469 |
newlib update - added zeroing of r0 to crt0.S |
julius |
4948d 12h |
/openrisc/ |
468 |
ORPSoC update:
Added USER_ELF and USER_VMEM options to reference design simulation scripts.
Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path
ML501's board.h bootrom default now boot from SPI |
julius |
4948d 12h |
/openrisc/ |