Rev |
Log message |
Author |
Age |
Path |
66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5325d 14h |
/openrisc/ |
65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5329d 20h |
/openrisc/ |
64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5332d 15h |
/openrisc/ |
63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5342d 12h |
/openrisc/ |
62 |
This material is part of the separate website downloads directory. |
jeremybennett |
5353d 15h |
/openrisc/ |
61 |
The build directory should not be part of the SVN configuration. |
jeremybennett |
5353d 16h |
/openrisc/ |
60 |
Mark Jarvin's patches to support Mac OS X (Snow Leopard). |
jeremybennett |
5360d 09h |
/openrisc/ |
59 |
Toolchain install script gcc patch change and gdb configure change |
julius |
5381d 09h |
/openrisc/ |
58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5384d 08h |
/openrisc/ |
57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5389d 12h |
/openrisc/ |
56 |
adding generic pll model to orpsoc |
julius |
5397d 14h |
/openrisc/ |
55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5400d 04h |
/openrisc/ |
54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5410d 11h |
/openrisc/ |
53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5428d 12h |
/openrisc/ |
52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5429d 08h |
/openrisc/ |
51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5443d 10h |
/openrisc/ |
50 |
Adding or32_funcs.S |
julius |
5443d 14h |
/openrisc/ |
49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5462d 04h |
/openrisc/ |
48 |
Adds an initialization to keep GCC happy in jp1_ll_read_jp1. |
jeremybennett |
5462d 07h |
/openrisc/ |
47 |
debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions |
julius |
5471d 15h |
/openrisc/ |
46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5477d 15h |
/openrisc/ |
45 |
Orpsoc eth test fix and script error message update |
julius |
5484d 15h |
/openrisc/ |
44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5513d 15h |
/openrisc/ |
43 |
Couple of fixes to ORPSoC, new linux patch version in toolchain script |
julius |
5537d 12h |
/openrisc/ |
42 |
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model |
julius |
5553d 09h |
/openrisc/ |
41 |
Update to or1k top |
julius |
5556d 10h |
/openrisc/ |
40 |
Added GDB server to verilog simulation via VPI and make target to build and run this model |
julius |
5557d 15h |
/openrisc/ |
39 |
Adding OR debug proxy a makefile tweak for uClibc and toolchain install script update |
julius |
5561d 16h |
/openrisc/ |
38 |
Adding binutils, gcc, uClibc patched source and patches |
julius |
5571d 15h |
/openrisc/ |
37 |
Update to the toolchain script - uses gcc-core package now instead of complete gcc |
julius |
5571d 16h |
/openrisc/ |