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678 added credits skrzyp 4490d 23h /openrisc/
677 atlys: add 2-clock synchronizer chain for ddr2_calib_done

The signal ddr2_calib_done signal comes from the ddr2 clock domain,
while wb_req is treating it as if it came from wb_clk domain. As a
result the timing analysis tool assumed a worst case scenario of 5ns
between the two domains and the results were miserable.

While we can argue that this is a multi-cycle path, the fact is that
ddr2_calib_done feeds into multiple logic sinks and can potentially
cause meta-stability issue in the design. The solution is to add a
2-clock meta-stability filter to address both the timing problems and
the meta-stability concern.

Signed-off-by: Jason Zheng <jxzheng@gmail.com>
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Acked-by: Olof Kindgren <olof.kindgren@orsoc.se>
stekern 4498d 22h /openrisc/
676 Add a libgloss definition file for the new ORSoC OpenRISC development board

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Yann Vernier <yann.vernier at orsoc.se>
olof 4507d 04h /openrisc/
675 FreeRTOSV6.1.1
Source cleanup
Add redzone beyond the stack pointer
filepang 4529d 15h /openrisc/
674 or1200: Fix for Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled julius 4533d 05h /openrisc/
673 Multiple 64-bit fixes (mostly sign and size of constants). Fix bug #1. yannv 4566d 00h /openrisc/
672 ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled

OR1200 RTL fix and software test added.
julius 4569d 16h /openrisc/
671 ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression tests failing due to change in memory model julius 4569d 16h /openrisc/
670 Changing bugurl as we have bugzilla now olof 4569d 20h /openrisc/
669 FreeRTOSV6.1.1
source cleanup, delete uncecessary code
filepang 4573d 00h /openrisc/
668 FreeRTOSV6.1.1
add missing 'make clean' in make script
filepang 4573d 15h /openrisc/
667 Corrected ITLB/DTLB values according to the arch spec.
This partially fixes bug #58
olof 4574d 20h /openrisc/
666 FreeRTOSV6.1.1
minimal set of standard demo task is working
filepang 4576d 00h /openrisc/
665 FreeRTOSV6.1.1
fix context save/restore stack size bug
remove unnecessary line
filepang 4576d 00h /openrisc/
664 FreeRTOSV6.1.1
modify processor abstraction layer.
now,all tasks are running in supervisor mode
filepang 4576d 00h /openrisc/
663 Fix compatibility problems with GCC 4.6.1. Fix a bug with hardware floating point in GCC. jeremybennett 4579d 19h /openrisc/
662 minor corrections to clean simulation files paknick 4595d 21h /openrisc/
661 added makefile for icarus simulation paknick 4595d 21h /openrisc/
660 updated makefiles for simulation with altera ordb2a-ep4ce22 paknick 4595d 23h /openrisc/
659 Fixed longjmp hal implementation skrzyp 4598d 04h /openrisc/
658 example configuration uses RAM startup skrzyp 4616d 01h /openrisc/
657 test generation fixed skrzyp 4616d 03h /openrisc/
656 orpsoc: cfi_ctrl software driver fix to allow compilation when it's not used julius 4620d 18h /openrisc/
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4620d 18h /openrisc/
654 added eCos-3.0 port skrzyp 4621d 22h /openrisc/
653 Make gdb link to or1ksim's libsim last, so wrapper works yannv 4629d 00h /openrisc/
652 Fix make compile.tcl for actel backend yannv 4629d 01h /openrisc/
651 ORPSoC: The ability to use a free/gimped version of Modelsim was restricted to
the reference build's scripts. This patch adds support for it to the
scripts for the board builds as well.

Signed-off-by: Julius Baxter <julius at opencores.org>
acked-by: Stefan Kristiansson <stefan.kristiansson at saunalahti.fi>
julius 4633d 20h /openrisc/
650 ORPSoC: documentation update to fix explanation of Xilinx environment setup, add section for Atlys board, various cleanups julius 4634d 17h /openrisc/
649 porting some of standard demo tasks

fix serial port(UART) interrupt handler
filepang 4650d 23h /openrisc/

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