| Rev |
Log message |
Author |
Age |
Path |
| 71 |
ORPSoC board builds, adding readmes |
julius |
5227d 05h |
/openrisc/ |
| 70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5231d 10h |
/openrisc/ |
| 69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5231d 11h |
/openrisc/ |
| 68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5234d 02h |
/openrisc/ |
| 67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5234d 05h |
/openrisc/ |
| 66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5254d 03h |
/openrisc/ |
| 65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5258d 09h |
/openrisc/ |
| 64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5261d 04h |
/openrisc/ |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5271d 01h |
/openrisc/ |
| 62 |
This material is part of the separate website downloads directory. |
jeremybennett |
5282d 05h |
/openrisc/ |
| 61 |
The build directory should not be part of the SVN configuration. |
jeremybennett |
5282d 05h |
/openrisc/ |
| 60 |
Mark Jarvin's patches to support Mac OS X (Snow Leopard). |
jeremybennett |
5288d 22h |
/openrisc/ |
| 59 |
Toolchain install script gcc patch change and gdb configure change |
julius |
5309d 23h |
/openrisc/ |
| 58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5312d 21h |
/openrisc/ |
| 57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5318d 01h |
/openrisc/ |
| 56 |
adding generic pll model to orpsoc |
julius |
5326d 03h |
/openrisc/ |
| 55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5328d 18h |
/openrisc/ |
| 54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5339d 01h |
/openrisc/ |
| 53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5357d 01h |
/openrisc/ |
| 52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5357d 21h |
/openrisc/ |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5372d 00h |
/openrisc/ |
| 50 |
Adding or32_funcs.S |
julius |
5372d 04h |
/openrisc/ |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5390d 18h |
/openrisc/ |
| 48 |
Adds an initialization to keep GCC happy in jp1_ll_read_jp1. |
jeremybennett |
5390d 21h |
/openrisc/ |
| 47 |
debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions |
julius |
5400d 04h |
/openrisc/ |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5406d 05h |
/openrisc/ |
| 45 |
Orpsoc eth test fix and script error message update |
julius |
5413d 04h |
/openrisc/ |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5442d 04h |
/openrisc/ |
| 43 |
Couple of fixes to ORPSoC, new linux patch version in toolchain script |
julius |
5466d 01h |
/openrisc/ |
| 42 |
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model |
julius |
5481d 22h |
/openrisc/ |
