Rev |
Log message |
Author |
Age |
Path |
77 |
Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour |
rherveille |
5235d 16h |
/openrisc/ |
76 |
Added: +libext+.v
Added: +incdir+. |
rherveille |
5236d 16h |
/openrisc/ |
75 |
Fixed toolchain script's cygwin ncurses check |
julius |
5241d 18h |
/openrisc/ |
74 |
Toolchain script fix for ncurses header checking |
julius |
5259d 21h |
/openrisc/ |
73 |
toolchain script error fix |
julius |
5259d 22h |
/openrisc/ |
72 |
Toolchain install script: or1ksim location changed, few tweaks |
julius |
5262d 19h |
/openrisc/ |
71 |
ORPSoC board builds, adding readmes |
julius |
5279d 02h |
/openrisc/ |
70 |
ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! |
julius |
5283d 06h |
/openrisc/ |
69 |
ORPSoC xilinx ml501 board update - added ethernet eupport and software test |
julius |
5283d 07h |
/openrisc/ |
68 |
Fixed up a couple of Makefile things in ORPSoCv2 |
julius |
5285d 23h |
/openrisc/ |
67 |
New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory |
julius |
5286d 02h |
/openrisc/ |
66 |
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. |
julius |
5306d 00h |
/openrisc/ |
65 |
ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix |
julius |
5310d 06h |
/openrisc/ |
64 |
Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. |
julius |
5313d 01h |
/openrisc/ |
63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5322d 22h |
/openrisc/ |
62 |
This material is part of the separate website downloads directory. |
jeremybennett |
5334d 01h |
/openrisc/ |
61 |
The build directory should not be part of the SVN configuration. |
jeremybennett |
5334d 02h |
/openrisc/ |
60 |
Mark Jarvin's patches to support Mac OS X (Snow Leopard). |
jeremybennett |
5340d 19h |
/openrisc/ |
59 |
Toolchain install script gcc patch change and gdb configure change |
julius |
5361d 19h |
/openrisc/ |
58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5364d 18h |
/openrisc/ |
57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5369d 22h |
/openrisc/ |
56 |
adding generic pll model to orpsoc |
julius |
5378d 00h |
/openrisc/ |
55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5380d 14h |
/openrisc/ |
54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5390d 21h |
/openrisc/ |
53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5408d 22h |
/openrisc/ |
52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5409d 18h |
/openrisc/ |
51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5423d 20h |
/openrisc/ |
50 |
Adding or32_funcs.S |
julius |
5424d 00h |
/openrisc/ |
49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5442d 14h |
/openrisc/ |
48 |
Adds an initialization to keep GCC happy in jp1_ll_read_jp1. |
jeremybennett |
5442d 17h |
/openrisc/ |